1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
|
/**********************************************************************
* Author: Cavium Networks
*
* Contact: support@caviumnetworks.com
* This file is part of the OCTEON SDK
*
* Copyright (c) 2003-2007 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful, but
* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
* NONINFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this file; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* or visit http://www.gnu.org/licenses/.
*
* This file may also be available under a different license from Cavium.
* Contact Cavium Networks for more information
**********************************************************************/
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <net/dst.h>
#include <asm/octeon/octeon.h>
#include "ethernet-defines.h"
#include "octeon-ethernet.h"
#include "ethernet-util.h"
#include "cvmx-spi.h"
#include <asm/octeon/cvmx-npi-defs.h>
#include "cvmx-spxx-defs.h"
#include "cvmx-stxx-defs.h"
static int number_spi_ports;
static int need_retrain[2] = { 0, 0 };
static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id)
{
irqreturn_t return_status = IRQ_NONE;
union cvmx_npi_rsl_int_blocks rsl_int_blocks;
/* Check and see if this interrupt was caused by the GMX block */
rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
if (rsl_int_blocks.s.spx1) { /* 19 - SPX1_INT_REG & STX1_INT_REG */
union cvmx_spxx_int_reg spx_int_reg;
union cvmx_stxx_int_reg stx_int_reg;
spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1));
cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64);
if (!need_retrain[1]) {
spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
if (spx_int_reg.s.spf)
pr_err("SPI1: SRX Spi4 interface down\n");
if (spx_int_reg.s.calerr)
pr_err("SPI1: SRX Spi4 Calendar table "
"parity error\n");
if (spx_int_reg.s.syncerr)
pr_err("SPI1: SRX Consecutive Spi4 DIP4 "
"errors have exceeded "
"SPX_ERR_CTL[ERRCNT]\n");
if (spx_int_reg.s.diperr)
pr_err("SPI1: SRX Spi4 DIP4 error\n");
if (spx_int_reg.s.tpaovr)
pr_err("SPI1: SRX Selected port has hit "
"TPA overflow\n");
if (spx_int_reg.s.rsverr)
pr_err("SPI1: SRX Spi4 reserved control "
"word detected\n");
if (spx_int_reg.s.drwnng)
pr_err("SPI1: SRX Spi4 receive FIFO "
"drowning/overflow\n");
if (spx_int_reg.s.clserr)
pr_err("SPI1: SRX Spi4 packet closed on "
"non-16B alignment without EOP\n");
if (spx_int_reg.s.spiovr)
pr_err("SPI1: SRX Spi4 async FIFO overflow\n");
if (spx_int_reg.s.abnorm)
pr_err("SPI1: SRX Abnormal packet "
"termination (ERR bit)\n");
if (spx_int_reg.s.prtnxa)
pr_err("SPI1: SRX Port out of range\n");
}
stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1));
cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64);
if (!need_retrain[1]) {
stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
if (stx_int_reg.s.syncerr)
pr_err("SPI1: STX Interface encountered a "
"fatal error\n");
if (stx_int_reg.s.frmerr)
pr_err("SPI1: STX FRMCNT has exceeded "
"STX_DIP_CNT[MAXFRM]\n");
if (stx_int_reg.s.unxfrm)
pr_err("SPI1: STX Unexpected framing "
"sequence\n");
if (stx_int_reg.s.nosync)
pr_err("SPI1: STX ERRCNT has exceeded "
"STX_DIP_CNT[MAXDIP]\n");
if (stx_int_reg.s.diperr)
pr_err("SPI1: STX DIP2 error on the Spi4 "
"Status channel\n");
if (stx_int_reg.s.datovr)
pr_err("SPI1: STX Spi4 FIFO overflow error\n");
if (stx_int_reg.s.ovrbst)
pr_err("SPI1: STX Transmit packet burst "
"too big\n");
if (stx_int_reg.s.calpar1)
pr_err("SPI1: STX Calendar Table Parity "
"Error Bank1\n");
if (stx_int_reg.s.calpar0)
pr_err("SPI1: STX Calendar Table Parity "
"Error Bank0\n");
}
cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0);
cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0);
need_retrain[1] = 1;
return_status = IRQ_HANDLED;
}
if (rsl_int_blocks.s.spx0) { /* 18 - SPX0_INT_REG & STX0_INT_REG */
union cvmx_spxx_int_reg spx_int_reg;
union cvmx_stxx_int_reg stx_int_reg;
spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0));
cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64);
if (!need_retrain[0]) {
spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
if (spx_int_reg.s.spf)
pr_err("SPI0: SRX Spi4 interface down\n");
if (spx_int_reg.s.calerr)
pr_err("SPI0: SRX Spi4 Calendar table "
"parity error\n");
if (spx_int_reg.s.syncerr)
pr_err("SPI0: SRX Consecutive Spi4 DIP4 "
"errors have exceeded "
"SPX_ERR_CTL[ERRCNT]\n");
if (spx_int_reg.s.diperr)
pr_err("SPI0: SRX Spi4 DIP4 error\n");
if (spx_int_reg.s.tpaovr)
pr_err("SPI0: SRX Selected port has hit "
"TPA overflow\n");
if (spx_int_reg.s.rsverr)
pr_err("SPI0: SRX Spi4 reserved control "
"word detected\n");
if (spx_int_reg.s.drwnng)
pr_err("SPI0: SRX Spi4 receive FIFO "
"drowning/overflow\n");
if (spx_int_reg.s.clserr)
pr_err("SPI0: SRX Spi4 packet closed on "
"non-16B alignment without EOP\n");
if (spx_int_reg.s.spiovr)
pr_err("SPI0: SRX Spi4 async FIFO overflow\n");
if (spx_int_reg.s.abnorm)
pr_err("SPI0: SRX Abnormal packet "
"termination (ERR bit)\n");
if (spx_int_reg.s.prtnxa)
pr_err("SPI0: SRX Port out of range\n");
}
stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0));
cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64);
if (!need_retrain[0]) {
stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
if (stx_int_reg.s.syncerr)
pr_err("SPI0: STX Interface encountered a "
"fatal error\n");
if (stx_int_reg.s.frmerr)
pr_err("SPI0: STX FRMCNT has exceeded "
"STX_DIP_CNT[MAXFRM]\n");
if (stx_int_reg.s.unxfrm)
pr_err("SPI0: STX Unexpected framing "
"sequence\n");
if (stx_int_reg.s.nosync)
pr_err("SPI0: STX ERRCNT has exceeded "
"STX_DIP_CNT[MAXDIP]\n");
if (stx_int_reg.s.diperr)
pr_err("SPI0: STX DIP2 error on the Spi4 "
"Status channel\n");
if (stx_int_reg.s.datovr)
pr_err("SPI0: STX Spi4 FIFO overflow error\n");
if (stx_int_reg.s.ovrbst)
pr_err("SPI0: STX Transmit packet burst "
"too big\n");
if (stx_int_reg.s.calpar1)
pr_err("SPI0: STX Calendar Table Parity "
"Error Bank1\n");
if (stx_int_reg.s.calpar0)
pr_err("SPI0: STX Calendar Table Parity "
"Error Bank0\n");
}
cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0);
cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0);
need_retrain[0] = 1;
return_status = IRQ_HANDLED;
}
return return_status;
}
static void cvm_oct_spi_enable_error_reporting(int interface)
{
union cvmx_spxx_int_msk spxx_int_msk;
union cvmx_stxx_int_msk stxx_int_msk;
spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
spxx_int_msk.s.calerr = 1;
spxx_int_msk.s.syncerr = 1;
spxx_int_msk.s.diperr = 1;
spxx_int_msk.s.tpaovr = 1;
spxx_int_msk.s.rsverr = 1;
spxx_int_msk.s.drwnng = 1;
spxx_int_msk.s.clserr = 1;
spxx_int_msk.s.spiovr = 1;
spxx_int_msk.s.abnorm = 1;
spxx_int_msk.s.prtnxa = 1;
cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
stxx_int_msk.s.frmerr = 1;
stxx_int_msk.s.unxfrm = 1;
stxx_int_msk.s.nosync = 1;
stxx_int_msk.s.diperr = 1;
stxx_int_msk.s.datovr = 1;
stxx_int_msk.s.ovrbst = 1;
stxx_int_msk.s.calpar1 = 1;
stxx_int_msk.s.calpar0 = 1;
cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
}
static void cvm_oct_spi_poll(struct net_device *dev)
{
static int spi4000_port;
struct octeon_ethernet *priv = netdev_priv(dev);
int interface;
for (interface = 0; interface < 2; interface++) {
if ((priv->port == interface * 16) && need_retrain[interface]) {
if (cvmx_spi_restart_interface
(interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) {
need_retrain[interface] = 0;
cvm_oct_spi_enable_error_reporting(interface);
}
}
/*
* The SPI4000 TWSI interface is very slow. In order
* not to bring the system to a crawl, we only poll a
* single port every second. This means negotiation
* speed changes take up to 10 seconds, but at least
* we don't waste absurd amounts of time waiting for
* TWSI.
*/
if (priv->port == spi4000_port) {
/*
* This function does nothing if it is called on an
* interface without a SPI4000.
*/
cvmx_spi4000_check_speed(interface, priv->port);
/*
* Normal ordering increments. By decrementing
* we only match once per iteration.
*/
spi4000_port--;
if (spi4000_port < 0)
spi4000_port = 10;
}
}
}
int cvm_oct_spi_init(struct net_device *dev)
{
int r;
struct octeon_ethernet *priv = netdev_priv(dev);
if (number_spi_ports == 0) {
r = request_irq(OCTEON_IRQ_RML, cvm_oct_spi_rml_interrupt,
IRQF_SHARED, "SPI", &number_spi_ports);
}
number_spi_ports++;
if ((priv->port == 0) || (priv->port == 16)) {
cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
priv->poll = cvm_oct_spi_poll;
}
cvm_oct_common_init(dev);
return 0;
}
void cvm_oct_spi_uninit(struct net_device *dev)
{
int interface;
cvm_oct_common_uninit(dev);
number_spi_ports--;
if (number_spi_ports == 0) {
for (interface = 0; interface < 2; interface++) {
cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
}
free_irq(OCTEON_IRQ_RML, &number_spi_ports);
}
}
|
