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authorBen Skeggs <darktama@iinet.net.au>2006-10-14 06:57:49 +1100
committerBen Skeggs <darktama@iinet.net.au>2006-10-14 06:57:49 +1100
commit4988074794531939ec0cb0ad183633b59e9ccff4 (patch)
tree4bc58b1c23885d9288494219b71666db4c204c1d
parenta9c6c3f21d90257db94536f202b3a1f03896b2f7 (diff)
Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals). Ch 1 GET now advances, but no ctx_switch.
-rw-r--r--shared-core/nouveau_fifo.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c
index 1761bbec..bd924f5f 100644
--- a/shared-core/nouveau_fifo.c
+++ b/shared-core/nouveau_fifo.c
@@ -259,6 +259,10 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
#endif
}
+ /* disable the pusher ? */
+ NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0);
+ NV_WRITE(NV_PFIFO_CACH1_PSH0, 0);
+
/* enable the fifo dma operation */
NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
@@ -274,6 +278,10 @@ static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init,
NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
+ /* reenable the pusher ? */
+ NV_WRITE(NV_PFIFO_CACH1_PSH0, 1);
+ NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 1);
+
/* reenable the fifo caches */
NV_WRITE(NV_PFIFO_CACHES, 0x00000001);