remove obsolete files

17 files changed, 0 insertions, 12306 deletions

diff --git a/bsd/gamma/gamma_dma.c b/bsd/gamma/gamma_dma.c
deleted file mode 100644
index 0dee8c74..00000000
--- a/bsd/gamma/gamma_dma.c
+++ /dev/null
@@ -1,568 +0,0 @@
-/* gamma_dma.c -- DMA support for GMX 2000 -*- linux-c -*-
- * Created: Fri Mar 19 14:30:16 1999 by faith@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *
- */
-
-
-
-#include "gamma.h"
-#include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
-#include "gamma_drv.h"
-
-
-static __inline__ void gamma_dma_dispatch(drm_device_t *dev, unsigned long address,
-				      unsigned long length)
-{
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	GAMMA_WRITE(GAMMA_DMAADDRESS, DRM_OS_VTOPHYS((void *)address));
-	while (GAMMA_READ(GAMMA_GCOMMANDSTATUS) != 4)
-		;
-	GAMMA_WRITE(GAMMA_DMACOUNT, length / 4);
-}
-
-void gamma_dma_quiescent_single(drm_device_t *dev)
-{
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	while (GAMMA_READ(GAMMA_DMACOUNT))
-		;
-	while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
-		;
-
-	GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
-	GAMMA_WRITE(GAMMA_SYNC, 0);
-
-	do {
-		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
-			;
-	} while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
-}
-
-void gamma_dma_quiescent_dual(drm_device_t *dev)
-{
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	while (GAMMA_READ(GAMMA_DMACOUNT))
-		;
-	while (GAMMA_READ(GAMMA_INFIFOSPACE) < 3)
-		;
-
-	GAMMA_WRITE(GAMMA_BROADCASTMASK, 3);
-
-	GAMMA_WRITE(GAMMA_FILTERMODE, 1 << 10);
-	GAMMA_WRITE(GAMMA_SYNC, 0);
-
-				/* Read from first MX */
-	do {
-		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS))
-			;
-	} while (GAMMA_READ(GAMMA_OUTPUTFIFO) != GAMMA_SYNC_TAG);
-
-				/* Read from second MX */
-	do {
-		while (!GAMMA_READ(GAMMA_OUTFIFOWORDS + 0x10000))
-			;
-	} while (GAMMA_READ(GAMMA_OUTPUTFIFO + 0x10000) != GAMMA_SYNC_TAG);
-}
-
-void gamma_dma_ready(drm_device_t *dev)
-{
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	while (GAMMA_READ(GAMMA_DMACOUNT))
-		;
-}
-
-static __inline__ int gamma_dma_is_ready(drm_device_t *dev)
-{
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	return !GAMMA_READ(GAMMA_DMACOUNT);
-}
-
-void gamma_dma_service( DRM_OS_IRQ_ARGS)
-{
-	drm_device_t	    *dev      = (drm_device_t *)device;
-	drm_device_dma_t    *dma      = dev->dma;
-	drm_gamma_private_t *dev_priv =
-		(drm_gamma_private_t *)dev->dev_private;
-
-	atomic_inc(&dev->counts[6]); /* _DRM_STAT_IRQ */
-	GAMMA_WRITE(GAMMA_GDELAYTIMER, 0xc350/2); /* 0x05S */
-	GAMMA_WRITE(GAMMA_GCOMMANDINTFLAGS, 8);
-	GAMMA_WRITE(GAMMA_GINTFLAGS, 0x2001);
-	if (gamma_dma_is_ready(dev)) {
-				/* Free previous buffer */
-		if (test_and_set_bit(0, &dev->dma_flag)) return;
-		if (dma->this_buffer) {
-			gamma_free_buffer(dev, dma->this_buffer);
-			dma->this_buffer = NULL;
-		}
-		clear_bit(0, &dev->dma_flag);
-
-	}
-}
-
-/* Only called by gamma_dma_schedule. */
-static int gamma_do_dma(drm_device_t *dev, int locked)
-{
-	unsigned long	 address;
-	unsigned long	 length;
-	drm_buf_t	 *buf;
-	int		 retcode = 0;
-	drm_device_dma_t *dma = dev->dma;
-#if DRM_DMA_HISTOGRAM
-	cycles_t	 dma_start, dma_stop;
-#endif
-
-	if (test_and_set_bit(0, &dev->dma_flag)) DRM_OS_RETURN( EBUSY );
-
-#if DRM_DMA_HISTOGRAM
-	dma_start = get_cycles();
-#endif
-
-	if (!dma->next_buffer) {
-		DRM_ERROR("No next_buffer\n");
-		clear_bit(0, &dev->dma_flag);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf	= dma->next_buffer;
-	address = (unsigned long)buf->address;
-	length	= buf->used;
-
-	DRM_DEBUG("context %d, buffer %d (%ld bytes)\n",
-		  buf->context, buf->idx, length);
-
-	if (buf->list == DRM_LIST_RECLAIM) {
-		gamma_clear_next_buffer(dev);
-		gamma_free_buffer(dev, buf);
-		clear_bit(0, &dev->dma_flag);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if (!length) {
-		DRM_ERROR("0 length buffer\n");
-		gamma_clear_next_buffer(dev);
-		gamma_free_buffer(dev, buf);
-		clear_bit(0, &dev->dma_flag);
-		return 0;
-	}
-
-	if (!gamma_dma_is_ready(dev)) {
-		clear_bit(0, &dev->dma_flag);
-		DRM_OS_RETURN( EBUSY );
-	}
-
-	if (buf->while_locked) {
-		if (!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-			DRM_ERROR("Dispatching buffer %d from pid %d"
-				  " \"while locked\", but no lock held\n",
-				  buf->idx, buf->pid);
-		}
-	} else {
-		if (!locked && !gamma_lock_take(&dev->lock.hw_lock->lock,
-					      DRM_KERNEL_CONTEXT)) {
-			clear_bit(0, &dev->dma_flag);
-			DRM_OS_RETURN( EBUSY );
-		}
-	}
-
-	if (dev->last_context != buf->context
-	    && !(dev->queuelist[buf->context]->flags
-		 & _DRM_CONTEXT_PRESERVED)) {
-				/* PRE: dev->last_context != buf->context */
-		if (DRM(context_switch)(dev, dev->last_context,
-					buf->context)) {
-			DRM(clear_next_buffer)(dev);
-			DRM(free_buffer)(dev, buf);
-		}
-		retcode = EBUSY;
-		goto cleanup;
-
-				/* POST: we will wait for the context
-				   switch and will dispatch on a later call
-				   when dev->last_context == buf->context.
-				   NOTE WE HOLD THE LOCK THROUGHOUT THIS
-				   TIME! */
-	}
-
-	gamma_clear_next_buffer(dev);
-	buf->pending	 = 1;
-	buf->waiting	 = 0;
-	buf->list	 = DRM_LIST_PEND;
-#if DRM_DMA_HISTOGRAM
-	buf->time_dispatched = get_cycles();
-#endif
-
-	gamma_dma_dispatch(dev, address, length);
-	gamma_free_buffer(dev, dma->this_buffer);
-	dma->this_buffer = buf;
-
-	atomic_inc(&dev->counts[7]); /* _DRM_STAT_DMA */
-	atomic_add(length, &dev->counts[8]); /* _DRM_STAT_PRIMARY */
-
-	if (!buf->while_locked && !dev->context_flag && !locked) {
-		if (gamma_lock_free(dev, &dev->lock.hw_lock->lock,
-				  DRM_KERNEL_CONTEXT)) {
-			DRM_ERROR("\n");
-		}
-	}
-cleanup:
-
-	clear_bit(0, &dev->dma_flag);
-
-#if DRM_DMA_HISTOGRAM
-	dma_stop = get_cycles();
-	atomic_inc(&dev->histo.dma[gamma_histogram_slot(dma_stop - dma_start)]);
-#endif
-
-	DRM_OS_RETURN( retcode );
-}
-
-static void gamma_dma_timer_bh(unsigned long dev)
-{
-	gamma_dma_schedule((drm_device_t *)dev, 0);
-}
-
-void gamma_dma_immediate_bh(DRM_OS_TASKQUEUE_ARGS)
-{
-	gamma_dma_schedule(dev, 0);
-}
-
-int gamma_dma_schedule(drm_device_t *dev, int locked)
-{
-	int		 next;
-	drm_queue_t	 *q;
-	drm_buf_t	 *buf;
-	int		 retcode   = 0;
-	int		 processed = 0;
-	int		 missed;
-	int		 expire	   = 20;
-	drm_device_dma_t *dma	   = dev->dma;
-#if DRM_DMA_HISTOGRAM
-	cycles_t	 schedule_start;
-#endif
-
-	if (test_and_set_bit(0, &dev->interrupt_flag)) {
-				/* Not reentrant */
-		atomic_inc(&dev->counts[10]); /* _DRM_STAT_MISSED */
-		DRM_OS_RETURN( EBUSY );
-	}
-	missed = atomic_read(&dev->counts[10]);
-
-#if DRM_DMA_HISTOGRAM
-	schedule_start = get_cycles();
-#endif
-
-again:
-	if (dev->context_flag) {
-		clear_bit(0, &dev->interrupt_flag);
-		DRM_OS_RETURN( EBUSY );
-	}
-	if (dma->next_buffer) {
-				/* Unsent buffer that was previously
-				   selected, but that couldn't be sent
-				   because the lock could not be obtained
-				   or the DMA engine wasn't ready.  Try
-				   again. */
-		if (!(retcode = gamma_do_dma(dev, locked))) ++processed;
-	} else {
-		do {
-			next = gamma_select_queue(dev, gamma_dma_timer_bh);
-			if (next >= 0) {
-				q   = dev->queuelist[next];
-				buf = gamma_waitlist_get(&q->waitlist);
-				dma->next_buffer = buf;
-				dma->next_queue	 = q;
-				if (buf && buf->list == DRM_LIST_RECLAIM) {
-					gamma_clear_next_buffer(dev);
-					gamma_free_buffer(dev, buf);
-				}
-			}
-		} while (next >= 0 && !dma->next_buffer);
-		if (dma->next_buffer) {
-			if (!(retcode = gamma_do_dma(dev, locked))) {
-				++processed;
-			}
-		}
-	}
-
-	if (--expire) {
-		if (missed != atomic_read(&dev->counts[10])) {
-			if (gamma_dma_is_ready(dev)) goto again;
-		}
-		if (processed && gamma_dma_is_ready(dev)) {
-			processed = 0;
-			goto again;
-		}
-	}
-
-	clear_bit(0, &dev->interrupt_flag);
-
-#if DRM_DMA_HISTOGRAM
-	atomic_inc(&dev->histo.schedule[gamma_histogram_slot(get_cycles()
-							   - schedule_start)]);
-#endif
-	return retcode;
-}
-
-static int gamma_dma_priority(drm_device_t *dev, drm_dma_t *d)
-{
-	unsigned long	  address;
-	unsigned long	  length;
-	int		  must_free = 0;
-	int		  retcode   = 0;
-	int		  i;
-	int		  idx;
-	drm_buf_t	  *buf;
-	drm_buf_t	  *last_buf = NULL;
-	drm_device_dma_t  *dma	    = dev->dma;
-	static int never;
-
-				/* Turn off interrupt handling */
-	while (test_and_set_bit(0, &dev->interrupt_flag)) {
-		retcode = tsleep(&never, PZERO|PCATCH, "gamp1", 1);
-		if (retcode)
-			return retcode;
-	}
-	if (!(d->flags & _DRM_DMA_WHILE_LOCKED)) {
-		while (!gamma_lock_take(&dev->lock.hw_lock->lock,
-				      DRM_KERNEL_CONTEXT)) {
-			retcode = tsleep(&never, PZERO|PCATCH, "gamp2", 1);
-			if (retcode)
-				return retcode;
-		}
-		++must_free;
-	}
-
-	for (i = 0; i < d->send_count; i++) {
-		idx = d->send_indices[i];
-		if (idx < 0 || idx >= dma->buf_count) {
-			DRM_ERROR("Index %d (of %d max)\n",
-				  d->send_indices[i], dma->buf_count - 1);
-			continue;
-		}
-		buf = dma->buflist[ idx ];
-		if (buf->pid != DRM_OS_CURRENTPID) {
-			DRM_ERROR("Process %d using buffer owned by %d\n",
-				  DRM_OS_CURRENTPID, buf->pid);
-			retcode = EINVAL;
-			goto cleanup;
-		}
-		if (buf->list != DRM_LIST_NONE) {
-			DRM_ERROR("Process %d using %d's buffer on list %d\n",
-				  DRM_OS_CURRENTPID, buf->pid, buf->list);
-			retcode = EINVAL;
-			goto cleanup;
-		}
-				/* This isn't a race condition on
-				   buf->list, since our concern is the
-				   buffer reclaim during the time the
-				   process closes the /dev/drm? handle, so
-				   it can't also be doing DMA. */
-		buf->list	  = DRM_LIST_PRIO;
-		buf->used	  = d->send_sizes[i];
-		buf->context	  = d->context;
-		buf->while_locked = d->flags & _DRM_DMA_WHILE_LOCKED;
-		address		  = (unsigned long)buf->address;
-		length		  = buf->used;
-		if (!length) {
-			DRM_ERROR("0 length buffer\n");
-		}
-		if (buf->pending) {
-			DRM_ERROR("Sending pending buffer:"
-				  " buffer %d, offset %d\n",
-				  d->send_indices[i], i);
-			retcode = EINVAL;
-			goto cleanup;
-		}
-		if (buf->waiting) {
-			DRM_ERROR("Sending waiting buffer:"
-				  " buffer %d, offset %d\n",
-				  d->send_indices[i], i);
-			retcode = EINVAL;
-			goto cleanup;
-		}
-		buf->pending = 1;
-
-		if (dev->last_context != buf->context
-		    && !(dev->queuelist[buf->context]->flags
-			 & _DRM_CONTEXT_PRESERVED)) {
-			/* PRE: dev->last_context != buf->context */
-			DRM(context_switch)(dev, dev->last_context,
-					    buf->context);
-				/* POST: we will wait for the context
-				   switch and will dispatch on a later call
-				   when dev->last_context == buf->context.
-				   NOTE WE HOLD THE LOCK THROUGHOUT THIS
-				   TIME! */
-			retcode = tsleep(&dev->context_wait,  PZERO|PCATCH,
-				       "gamctx", 0);
-			if (retcode)
-				goto cleanup;
-			if (dev->last_context != buf->context) {
-				DRM_ERROR("Context mismatch: %d %d\n",
-					  dev->last_context,
-					  buf->context);
-			}
-		}
-
-#if DRM_DMA_HISTOGRAM
-		buf->time_queued     = get_cycles();
-		buf->time_dispatched = buf->time_queued;
-#endif
-		gamma_dma_dispatch(dev, address, length);
-		atomic_inc(&dev->counts[9]); /* _DRM_STAT_SPECIAL */
-		atomic_add(length, &dev->counts[8]); /* _DRM_STAT_PRIMARY */
-
-		if (last_buf) {
-			gamma_free_buffer(dev, last_buf);
-		}
-		last_buf = buf;
-	}
-
-
-cleanup:
-	if (last_buf) {
-		gamma_dma_ready(dev);
-		gamma_free_buffer(dev, last_buf);
-	}
-
-	if (must_free && !dev->context_flag) {
-		if (gamma_lock_free(dev, &dev->lock.hw_lock->lock,
-				  DRM_KERNEL_CONTEXT)) {
-			DRM_ERROR("\n");
-		}
-	}
-	clear_bit(0, &dev->interrupt_flag);
-	DRM_OS_RETURN( retcode );
-}
-
-static int gamma_dma_send_buffers(drm_device_t *dev, drm_dma_t *d)
-{
-	drm_buf_t	  *last_buf = NULL;
-	int		  retcode   = 0;
-	drm_device_dma_t  *dma	    = dev->dma;
-
-	if (d->flags & _DRM_DMA_BLOCK) {
-		last_buf = dma->buflist[d->send_indices[d->send_count-1]];
-		atomic_inc(&last_buf->dma_wait);
-	}
-
-	if ((retcode = gamma_dma_enqueue(dev, d))) {
-		if (d->flags & _DRM_DMA_BLOCK)
-			atomic_dec(&last_buf->dma_wait);
-		return retcode;
-	}
-
-	gamma_dma_schedule(dev, 0);
-
-	if (d->flags & _DRM_DMA_BLOCK) {
-		DRM_DEBUG("%d waiting\n", DRM_OS_CURRENTPID);
-		for (;;) {
-			retcode = tsleep(&last_buf->dma_wait, PZERO|PCATCH,
-					 "gamdw", 0);
-			if (!last_buf->waiting
-			    && !last_buf->pending)
-				break; /* finished */
-			if (retcode)
-				break;
-		}
-		atomic_dec(&last_buf->dma_wait);
-		DRM_DEBUG("%d running\n", DRM_OS_CURRENTPID);
-		if (!retcode
-		    || (last_buf->list==DRM_LIST_PEND && !last_buf->pending)) {
-			if (!last_buf->dma_wait) {
-				gamma_free_buffer(dev, last_buf);
-			}
-		}
-		if (retcode) {
-			DRM_ERROR("ctx%d w%d p%d c%d i%d l%d %d/%d\n",
-				  d->context,
-				  last_buf->waiting,
-				  last_buf->pending,
-				  DRM_WAITCOUNT(dev, d->context),
-				  last_buf->idx,
-				  last_buf->list,
-				  last_buf->pid,
-				  DRM_OS_CURRENTPID);
-		}
-	}
-	DRM_OS_RETURN( retcode );
-}
-
-int gamma_dma( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t  *dma	    = dev->dma;
-	int		  retcode   = 0;
-	drm_dma_t	  d;
-
-	DRM_OS_KRNFROMUSR(d, (drm_dma_t *) data, sizeof(d));
-
-	if (d.send_count < 0 || d.send_count > dma->buf_count) {
-		DRM_ERROR("Process %d trying to send %d buffers (of %d max)\n",
-			  DRM_OS_CURRENTPID, d.send_count, dma->buf_count);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if (d.request_count < 0 || d.request_count > dma->buf_count) {
-		DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
-			  DRM_OS_CURRENTPID, d.request_count, dma->buf_count);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if (d.send_count) {
-		if (d.flags & _DRM_DMA_PRIORITY)
-			retcode = gamma_dma_priority(dev, &d);
-		else
-			retcode = gamma_dma_send_buffers(dev, &d);
-	}
-
-	d.granted_count = 0;
-
-	if (!retcode && d.request_count) {
-		retcode = gamma_dma_get_buffers(dev, &d);
-	}
-
-	DRM_DEBUG("%d returning, granted = %d\n",
-		  DRM_OS_CURRENTPID, d.granted_count);
-	DRM_OS_KRNTOUSR((drm_dma_t *) data, d, sizeof(d));
-
-	return retcode;
-}
diff --git a/bsd/gamma/gamma_drv.c b/bsd/gamma/gamma_drv.c
deleted file mode 100644
index 50658bba..00000000
--- a/bsd/gamma/gamma_drv.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/* gamma.c -- 3dlabs GMX 2000 driver -*- linux-c -*-
- * Created: Mon Jan  4 08:58:31 1999 by faith@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#include <sys/types.h>
-#include <sys/bus.h>
-#include <pci/pcivar.h>
-#include <opt_drm_linux.h>
-#include "gamma.h"
-#include "drmP.h"
-#include "drm.h"
-#include "gamma_drm.h"
-#include "gamma_drv.h"
-
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"gamma"
-#define DRIVER_DESC		"3DLabs gamma"
-#define DRIVER_DATE		"20010216"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	0
-
-#define DRIVER_IOCTLS							  \
-	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	     = { gamma_dma,	  1, 0 }
-
-/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
- * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here.
- */
-drm_chipinfo_t DRM(devicelist)[] = {
-	{0x3d3d, 0x0008, 1, "3DLabs Gamma"},
-	{0, 0, 0, NULL}
-};
-
-
-#define __HAVE_COUNTERS		5
-#define __HAVE_COUNTER6		_DRM_STAT_IRQ
-#define __HAVE_COUNTER7		_DRM_STAT_DMA
-#define __HAVE_COUNTER8		_DRM_STAT_PRIMARY
-#define __HAVE_COUNTER9		_DRM_STAT_SPECIAL
-#define __HAVE_COUNTER10	_DRM_STAT_MISSED
-
-
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lists.h"
-#include "drm_lock.h"
-#include "drm_memory.h"
-#include "drm_vm.h"
-#include "drm_sysctl.h"
-
-DRIVER_MODULE(gamma, pci, gamma_driver, gamma_devclass, 0, 0);
diff --git a/bsd/i810/i810_dma.c b/bsd/i810/i810_dma.c
deleted file mode 100644
index 4310851a..00000000
--- a/bsd/i810/i810_dma.c
+++ /dev/null
@@ -1,1223 +0,0 @@
-/* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
- *	    Jeff Hartmann <jhartmann@valinux.com>
- *          Keith Whitwell <keithw@valinux.com>
- *
- */
-
-
-#include "i810.h"
-#include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
-#include "i810_drv.h"
-
-#define I810_BUF_FREE		2
-#define I810_BUF_CLIENT		1
-#define I810_BUF_HARDWARE      	0
-
-#define I810_BUF_UNMAPPED 0
-#define I810_BUF_MAPPED   1
-
-#define RING_LOCALS	unsigned int outring, ringmask; volatile char *virt;
-
-#define BEGIN_LP_RING(n) do {				\
-	if (I810_VERBOSE)				\
-		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
-			  n, __FUNCTION__);		\
-	if (dev_priv->ring.space < n*4) 		\
-		i810_wait_ring(dev, n*4);		\
-	dev_priv->ring.space -= n*4;			\
-	outring = dev_priv->ring.tail;			\
-	ringmask = dev_priv->ring.tail_mask;		\
-	virt = dev_priv->ring.virtual_start;		\
-} while (0)
-
-#define ADVANCE_LP_RING() do {					\
-	if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n");	\
-	dev_priv->ring.tail = outring;				\
-	I810_WRITE(LP_RING + RING_TAIL, outring);		\
-} while(0)
-
-#define OUT_RING(n) do {						\
-	if (I810_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
-	*(volatile unsigned int *)(virt + outring) = n;			\
-	outring += 4;							\
-	outring &= ringmask;						\
-} while (0);
-
-static __inline__ void i810_print_status_page(drm_device_t *dev)
-{
-   	drm_device_dma_t *dma = dev->dma;
-      	drm_i810_private_t *dev_priv = dev->dev_private;
-	u32 *temp = (u32 *)dev_priv->hw_status_page;
-   	int i;
-
-   	DRM_DEBUG(  "hw_status: Interrupt Status : %x\n", temp[0]);
-   	DRM_DEBUG(  "hw_status: LpRing Head ptr : %x\n", temp[1]);
-   	DRM_DEBUG(  "hw_status: IRing Head ptr : %x\n", temp[2]);
-      	DRM_DEBUG(  "hw_status: Reserved : %x\n", temp[3]);
-   	DRM_DEBUG(  "hw_status: Driver Counter : %d\n", temp[5]);
-   	for(i = 6; i < dma->buf_count + 6; i++) {
-	   	DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 6, temp[i]);
-	}
-}
-
-static drm_buf_t *i810_freelist_get(drm_device_t *dev)
-{
-   	drm_device_dma_t *dma = dev->dma;
-	int		 i;
-	char		failed;
-
-	/* Linear search might not be the best solution */
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-		/* In use is already a pointer */
-		_DRM_CAS(buf_priv->in_use, I810_BUF_FREE, I810_BUF_CLIENT,
-							failed);
-		if (!failed)
-			return buf;
-	}
-   	return NULL;
-}
-
-/* This should only be called if the buffer is not sent to the hardware
- * yet, the hardware updates in use for us once its on the ring buffer.
- */
-
-static int i810_freelist_put(drm_device_t *dev, drm_buf_t *buf)
-{
-   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-	char failed;
-
-   	/* In use is already a pointer */
-   	_DRM_CAS(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE, failed);
-	if(failed) {
-	   	DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
-	   	DRM_OS_RETURN( EINVAL );
-	}
-
-   	return 0;
-}
-
-#if 0
-int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
-{
-	DRM_OS_DEVICE;
-	drm_i810_private_t  *dev_priv;
-	drm_buf_t           *buf;
-	drm_i810_buf_priv_t *buf_priv;
-
-	lock_kernel();
-	dev_priv = dev->dev_private;
-	buf      = dev_priv->mmap_buffer;
-	buf_priv = buf->dev_private;
-
-	vma->vm_flags |= (VM_IO | VM_DONTCOPY);
-	vma->vm_file = filp;
-
-   	buf_priv->currently_mapped = I810_BUF_MAPPED;
-	unlock_kernel();
-
-	if (remap_page_range(vma->vm_start,
-			     VM_OFFSET(vma),
-			     vma->vm_end - vma->vm_start,
-			     vma->vm_page_prot)) DRM_OS_RETURN(EAGAIN);
-	return 0;
-}
-#endif
-
-static int i810_map_buffer(drm_buf_t *buf, struct file *filp)
-{
-	DRM_OS_DEVICE;
-	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-      	drm_i810_private_t *dev_priv = dev->dev_private;
-   	struct file_operations *old_fops;
-	int retcode = 0;
-
-	if(buf_priv->currently_mapped == I810_BUF_MAPPED) DRM_OS_RETURN(EINVAL);
-
-	if(VM_DONTCOPY != 0) {
-#if LINUX_VERSION_CODE <= 0x020402
-		down( &current->mm->mmap_sem );
-#else
-		down_write( &current->mm->mmap_sem );
-#endif
-		old_fops = filp->f_op;
-		filp->f_op = &i810_buffer_fops;
-		dev_priv->mmap_buffer = buf;
-		buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total,
-						    PROT_READ|PROT_WRITE,
-						    MAP_SHARED,
-						    buf->bus_address);
-		dev_priv->mmap_buffer = NULL;
-   		filp->f_op = old_fops;
-		if ((unsigned long)buf_priv->virtual > -1024UL) {
-			/* Real error */
-			DRM_DEBUG("mmap error\n");
-			retcode = (signed int)buf_priv->virtual;
-			buf_priv->virtual = 0;
-		}
-#if LINUX_VERSION_CODE <= 0x020402
-		up( &current->mm->mmap_sem );
-#else
-		up_write( &current->mm->mmap_sem );
-#endif
-	} else {
-		buf_priv->virtual = buf_priv->kernel_virtual;
-   		buf_priv->currently_mapped = I810_BUF_MAPPED;
-	}
-	return retcode;
-}
-
-static int i810_unmap_buffer(drm_buf_t *buf)
-{
-	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-	int retcode = 0;
-
-	if(VM_DONTCOPY != 0) {
-		if(buf_priv->currently_mapped != I810_BUF_MAPPED)
-			DRM_OS_RETURN(EINVAL);
-#if LINUX_VERSION_CODE <= 0x020402
-		down( &current->mm->mmap_sem );
-#else
-		down_write( &current->mm->mmap_sem );
-#endif
-        	retcode = do_munmap(current->mm,
-				    (unsigned long)buf_priv->virtual,
-				    (size_t) buf->total);
-#if LINUX_VERSION_CODE <= 0x020402
-		up( &current->mm->mmap_sem );
-#else
-		up_write( &current->mm->mmap_sem );
-#endif
-	}
-   	buf_priv->currently_mapped = I810_BUF_UNMAPPED;
-   	buf_priv->virtual = 0;
-
-	return retcode;
-}
-
-static int i810_dma_get_buffer(drm_device_t *dev, drm_i810_dma_t *d,
-			       struct file *filp)
-{
-	drm_file_t	  *priv	  = filp->private_data;
-	drm_buf_t	  *buf;
-	drm_i810_buf_priv_t *buf_priv;
-	int retcode = 0;
-
-	buf = i810_freelist_get(dev);
-	if (!buf) {
-		retcode = -ENOMEM;
-	   	DRM_DEBUG("retcode=%d\n", retcode);
-		DRM_OS_RETURN(retcode);
-	}
-
-	retcode = i810_map_buffer(buf, filp);
-	if(retcode) {
-		i810_freelist_put(dev, buf);
-	   	DRM_DEBUG("mapbuf failed, retcode %d\n", retcode);
-		return retcode;
-	}
-	buf->pid     = priv->pid;
-	buf_priv = buf->dev_private;
-	d->granted = 1;
-   	d->request_idx = buf->idx;
-   	d->request_size = buf->total;
-   	d->virtual = buf_priv->virtual;
-
-	return retcode;
-}
-
-static unsigned long i810_alloc_page(drm_device_t *dev)
-{
-	unsigned long address;
-
-	address = __get_free_page(GFP_KERNEL);
-	if(address == 0UL)
-		return 0;
-
-	atomic_inc(&virt_to_page(address)->count);
-	set_bit(PG_locked, &virt_to_page(address)->flags);
-
-	return address;
-}
-
-static void i810_free_page(drm_device_t *dev, unsigned long page)
-{
-	if(page == 0UL)
-		return;
-
-	atomic_dec(&virt_to_page(page)->count);
-	clear_bit(PG_locked, &virt_to_page(page)->flags);
-	DRM_OS_WAKEUP(&virt_to_page(page)->wait);
-	free_page(page);
-	return;
-}
-
-static int i810_dma_cleanup(drm_device_t *dev)
-{
-	drm_device_dma_t *dma = dev->dma;
-
-	if(dev->dev_private) {
-		int i;
-	   	drm_i810_private_t *dev_priv =
-	     		(drm_i810_private_t *) dev->dev_private;
-
-	   	if(dev_priv->ring.virtual_start) {
-		   	DRM(ioremapfree)((void *) dev_priv->ring.virtual_start,
-					 dev_priv->ring.Size);
-		}
-	   	if(dev_priv->hw_status_page != 0UL) {
-		   	i810_free_page(dev, dev_priv->hw_status_page);
-		   	/* Need to rewrite hardware status page */
-		   	I810_WRITE(0x02080, 0x1ffff000);
-		}
-	   	DRM(free)(dev->dev_private, sizeof(drm_i810_private_t),
-			 DRM_MEM_DRIVER);
-	   	dev->dev_private = NULL;
-
-		for (i = 0; i < dma->buf_count; i++) {
-			drm_buf_t *buf = dma->buflist[ i ];
-			drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-			DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total);
-		}
-	}
-   	return 0;
-}
-
-static int i810_wait_ring(drm_device_t *dev, int n)
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-   	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
-   	int iters = 0;
-   	unsigned long end;
-	unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-
-	end = jiffies + (HZ*3);
-   	while (ring->space < n) {
-	   	int i;
-
-	   	ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-	   	ring->space = ring->head - (ring->tail+8);
-		if (ring->space < 0) ring->space += ring->Size;
-
-		if (ring->head != last_head)
-		   end = jiffies + (HZ*3);
-
-	   	iters++;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("space: %d wanted %d\n", ring->space, n);
-		   	DRM_ERROR("lockup\n");
-		   	goto out_wait_ring;
-		}
-
-	   	for (i = 0 ; i < 2000 ; i++) ;
-	}
-
-out_wait_ring:
-   	return iters;
-}
-
-static void i810_kernel_lost_context(drm_device_t *dev)
-{
-      	drm_i810_private_t *dev_priv = dev->dev_private;
-   	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
-
-   	ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-     	ring->tail = I810_READ(LP_RING + RING_TAIL);
-     	ring->space = ring->head - (ring->tail+8);
-     	if (ring->space < 0) ring->space += ring->Size;
-}
-
-static int i810_freelist_init(drm_device_t *dev, drm_i810_private_t *dev_priv)
-{
-      	drm_device_dma_t *dma = dev->dma;
-   	int my_idx = 24;
-   	u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
-   	int i;
-
-   	if(dma->buf_count > 1019) {
-	   	/* Not enough space in the status page for the freelist */
-	   	DRM_OS_RETURN(EINVAL);
-	}
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-
-	   	buf_priv->in_use = hw_status++;
-	   	buf_priv->my_use_idx = my_idx;
-	   	my_idx += 4;
-
-	   	*buf_priv->in_use = I810_BUF_FREE;
-
-		buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address,
-							buf->total);
-	}
-	return 0;
-}
-
-static int i810_dma_initialize(drm_device_t *dev,
-			       drm_i810_private_t *dev_priv,
-			       drm_i810_init_t *init)
-{
-	drm_map_list_entry_t *listentry;
-
-   	memset(dev_priv, 0, sizeof(drm_i810_private_t));
-
-	TAILQ_FOREACH(listentry, dev->maplist, link) {
-		drm_map_t *map = listentry->map;
-		if (map->type == _DRM_SHM &&
-			map->flags & _DRM_CONTAINS_LOCK) {
-			dev_priv->sarea = map;
-			break;
-		}
-	}
-	
-	if(!dev_priv->sarea_map) {
-		dev->dev_private = (void *)dev_priv;
-	   	i810_dma_cleanup(dev);
-	   	DRM_ERROR("can not find sarea!\n");
-	   	DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->mmio_map, init->mmio_offset );
-	if(!dev_priv->mmio_map) {
-		dev->dev_private = (void *)dev_priv;
-	   	i810_dma_cleanup(dev);
-	   	DRM_ERROR("can not find mmio map!\n");
-	   	DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->buffer_map, init->buffers_offset );
-	if(!dev_priv->buffer_map) {
-		dev->dev_private = (void *)dev_priv;
-	   	i810_dma_cleanup(dev);
-	   	DRM_ERROR("can not find dma buffer map!\n");
-	   	DRM_OS_RETURN(EINVAL);
-	}
-
-	dev_priv->sarea_priv = (drm_i810_sarea_t *)
-		((u8 *)dev_priv->sarea_map->handle +
-		 init->sarea_priv_offset);
-
-   	atomic_set(&dev_priv->flush_done, 0);
-	init_waitqueue_head(&dev_priv->flush_queue);
-
-   	dev_priv->ring.Start = init->ring_start;
-   	dev_priv->ring.End = init->ring_end;
-   	dev_priv->ring.Size = init->ring_size;
-
-   	dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base +
-						    init->ring_start,
-						    init->ring_size);
-
-   	if (dev_priv->ring.virtual_start == NULL) {
-		dev->dev_private = (void *) dev_priv;
-	   	i810_dma_cleanup(dev);
-	   	DRM_ERROR("can not ioremap virtual address for"
-			  " ring buffer\n");
-	   	DRM_OS_RETURN(ENOMEM);
-	}
-
-   	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
-
-	dev_priv->w = init->w;
-	dev_priv->h = init->h;
-	dev_priv->pitch = init->pitch;
-	dev_priv->back_offset = init->back_offset;
-	dev_priv->depth_offset = init->depth_offset;
-
-	dev_priv->front_di1 = init->front_offset | init->pitch_bits;
-	dev_priv->back_di1 = init->back_offset | init->pitch_bits;
-	dev_priv->zi1 = init->depth_offset | init->pitch_bits;
-
-   	/* Program Hardware Status Page */
-   	dev_priv->hw_status_page = i810_alloc_page(dev);
-   	if(dev_priv->hw_status_page == 0UL) {
-		dev->dev_private = (void *)dev_priv;
-		i810_dma_cleanup(dev);
-		DRM_ERROR("Can not allocate hardware status page\n");
-		DRM_OS_RETURN(ENOMEM);
-	}
-   	memset((void *) dev_priv->hw_status_page, 0, PAGE_SIZE);
-   	DRM_DEBUG("hw status page @ %lx\n", dev_priv->hw_status_page);
-
-   	I810_WRITE(0x02080, virt_to_bus((void *)dev_priv->hw_status_page));
-   	DRM_DEBUG("Enabled hardware status page\n");
-
-   	/* Now we need to init our freelist */
-   	if(i810_freelist_init(dev, dev_priv) != 0) {
-		dev->dev_private = (void *)dev_priv;
-	   	i810_dma_cleanup(dev);
-	   	DRM_ERROR("Not enough space in the status page for"
-			  " the freelist\n");
-	   	DRM_OS_RETURN(ENOMEM);
-	}
-	dev->dev_private = (void *)dev_priv;
-
-   	return 0;
-}
-
-int i810_dma_init( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-   	drm_i810_private_t *dev_priv;
-   	drm_i810_init_t init;
-   	int retcode = 0;
-
-  	DRM_OS_KRNFROMUSR( init, (drm_i810_init_t *) data, sizeof(init) );
-
-   	switch(init.func) {
-	 	case I810_INIT_DMA:
-	   		dev_priv = DRM(alloc)(sizeof(drm_i810_private_t),
-					     DRM_MEM_DRIVER);
-	   		if(dev_priv == NULL) DRM_OS_RETURN(ENOMEM);
-	   		retcode = i810_dma_initialize(dev, dev_priv, &init);
-	   	break;
-	 	case I810_CLEANUP_DMA:
-	   		retcode = i810_dma_cleanup(dev);
-	   	break;
-	 	default:
-	   		retcode = -EINVAL;
-	   	break;
-	}
-
-   	DRM_OS_RETURN(retcode);
-}
-
-
-
-/* Most efficient way to verify state for the i810 is as it is
- * emitted.  Non-conformant state is silently dropped.
- *
- * Use 'volatile' & local var tmp to force the emitted values to be
- * identical to the verified ones.
- */
-static void i810EmitContextVerified( drm_device_t *dev,
-				     volatile unsigned int *code )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-	int i, j = 0;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I810_CTX_SETUP_SIZE );
-
-	OUT_RING( GFX_OP_COLOR_FACTOR );
-	OUT_RING( code[I810_CTXREG_CF1] );
-
-	OUT_RING( GFX_OP_STIPPLE );
-	OUT_RING( code[I810_CTXREG_ST1] );
-
-	for ( i = 4 ; i < I810_CTX_SETUP_SIZE ; i++ ) {
-		tmp = code[i];
-
-		if ((tmp & (7<<29)) == (3<<29) &&
-		    (tmp & (0x1f<<24)) < (0x1d<<24))
-		{
-			OUT_RING( tmp );
-			j++;
-		}
-	}
-
-	if (j & 1)
-		OUT_RING( 0 );
-
-	ADVANCE_LP_RING();
-}
-
-static void i810EmitTexVerified( drm_device_t *dev,
-				 volatile unsigned int *code )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-	int i, j = 0;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I810_TEX_SETUP_SIZE );
-
-	OUT_RING( GFX_OP_MAP_INFO );
-	OUT_RING( code[I810_TEXREG_MI1] );
-	OUT_RING( code[I810_TEXREG_MI2] );
-	OUT_RING( code[I810_TEXREG_MI3] );
-
-	for ( i = 4 ; i < I810_TEX_SETUP_SIZE ; i++ ) {
-		tmp = code[i];
-
-		if ((tmp & (7<<29)) == (3<<29) &&
-		    (tmp & (0x1f<<24)) < (0x1d<<24))
-		{
-			OUT_RING( tmp );
-			j++;
-		}
-	}
-
-	if (j & 1)
-		OUT_RING( 0 );
-
-	ADVANCE_LP_RING();
-}
-
-
-/* Need to do some additional checking when setting the dest buffer.
- */
-static void i810EmitDestVerified( drm_device_t *dev,
-				  volatile unsigned int *code )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I810_DEST_SETUP_SIZE + 2 );
-
-	tmp = code[I810_DESTREG_DI1];
-	if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
-		OUT_RING( CMD_OP_DESTBUFFER_INFO );
-		OUT_RING( tmp );
-	} else
-	   DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
-		     tmp, dev_priv->front_di1, dev_priv->back_di1);
-
-	/* invarient:
-	 */
-	OUT_RING( CMD_OP_Z_BUFFER_INFO );
-	OUT_RING( dev_priv->zi1 );
-
-	OUT_RING( GFX_OP_DESTBUFFER_VARS );
-	OUT_RING( code[I810_DESTREG_DV1] );
-
-	OUT_RING( GFX_OP_DRAWRECT_INFO );
-	OUT_RING( code[I810_DESTREG_DR1] );
-	OUT_RING( code[I810_DESTREG_DR2] );
-	OUT_RING( code[I810_DESTREG_DR3] );
-	OUT_RING( code[I810_DESTREG_DR4] );
-	OUT_RING( 0 );
-
-	ADVANCE_LP_RING();
-}
-
-
-
-static void i810EmitState( drm_device_t *dev )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	if (dirty & I810_UPLOAD_BUFFERS) {
-		i810EmitDestVerified( dev, sarea_priv->BufferState );
-		sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
-	}
-
-	if (dirty & I810_UPLOAD_CTX) {
-		i810EmitContextVerified( dev, sarea_priv->ContextState );
-		sarea_priv->dirty &= ~I810_UPLOAD_CTX;
-	}
-
-	if (dirty & I810_UPLOAD_TEX0) {
-		i810EmitTexVerified( dev, sarea_priv->TexState[0] );
-		sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
-	}
-
-	if (dirty & I810_UPLOAD_TEX1) {
-		i810EmitTexVerified( dev, sarea_priv->TexState[1] );
-		sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
-	}
-}
-
-
-
-/* need to verify
- */
-static void i810_dma_dispatch_clear( drm_device_t *dev, int flags,
-				     unsigned int clear_color,
-				     unsigned int clear_zval )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int pitch = dev_priv->pitch;
-	int cpp = 2;
-	int i;
-	RING_LOCALS;
-
-  	i810_kernel_lost_context(dev);
-
-      	if (nbox > I810_NR_SAREA_CLIPRECTS)
-     		nbox = I810_NR_SAREA_CLIPRECTS;
-
-	for (i = 0 ; i < nbox ; i++, pbox++) {
-		unsigned int x = pbox->x1;
-		unsigned int y = pbox->y1;
-		unsigned int width = (pbox->x2 - x) * cpp;
-		unsigned int height = pbox->y2 - y;
-		unsigned int start = y * pitch + x * cpp;
-
-		if (pbox->x1 > pbox->x2 ||
-		    pbox->y1 > pbox->y2 ||
-		    pbox->x2 > dev_priv->w ||
-		    pbox->y2 > dev_priv->h)
-			continue;
-
-	   	if ( flags & I810_FRONT ) {
-		   	DRM_DEBUG("clear front\n");
-			BEGIN_LP_RING( 6 );
-			OUT_RING( BR00_BITBLT_CLIENT |
-				  BR00_OP_COLOR_BLT | 0x3 );
-			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
-			OUT_RING( (height << 16) | width );
-			OUT_RING( start );
-			OUT_RING( clear_color );
-			OUT_RING( 0 );
-			ADVANCE_LP_RING();
-		}
-
-		if ( flags & I810_BACK ) {
-			DRM_DEBUG("clear back\n");
-			BEGIN_LP_RING( 6 );
-			OUT_RING( BR00_BITBLT_CLIENT |
-				  BR00_OP_COLOR_BLT | 0x3 );
-			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
-			OUT_RING( (height << 16) | width );
-			OUT_RING( dev_priv->back_offset + start );
-			OUT_RING( clear_color );
-			OUT_RING( 0 );
-			ADVANCE_LP_RING();
-		}
-
-		if ( flags & I810_DEPTH ) {
-			DRM_DEBUG("clear depth\n");
-			BEGIN_LP_RING( 6 );
-			OUT_RING( BR00_BITBLT_CLIENT |
-				  BR00_OP_COLOR_BLT | 0x3 );
-			OUT_RING( BR13_SOLID_PATTERN | (0xF0 << 16) | pitch );
-			OUT_RING( (height << 16) | width );
-			OUT_RING( dev_priv->depth_offset + start );
-			OUT_RING( clear_zval );
-			OUT_RING( 0 );
-			ADVANCE_LP_RING();
-		}
-	}
-}
-
-static void i810_dma_dispatch_swap( drm_device_t *dev )
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-      	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int pitch = dev_priv->pitch;
-	int cpp = 2;
-	int ofs = dev_priv->back_offset;
-	int i;
-	RING_LOCALS;
-
-	DRM_DEBUG("swapbuffers\n");
-
-  	i810_kernel_lost_context(dev);
-
-      	if (nbox > I810_NR_SAREA_CLIPRECTS)
-     		nbox = I810_NR_SAREA_CLIPRECTS;
-
-	for (i = 0 ; i < nbox; i++, pbox++)
-	{
-		unsigned int w = pbox->x2 - pbox->x1;
-		unsigned int h = pbox->y2 - pbox->y1;
-		unsigned int dst = pbox->x1*cpp + pbox->y1*pitch;
-		unsigned int start = ofs + dst;
-
-		if (pbox->x1 > pbox->x2 ||
-		    pbox->y1 > pbox->y2 ||
-		    pbox->x2 > dev_priv->w ||
-		    pbox->y2 > dev_priv->h)
-			continue;
-
-	   	DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
-			  pbox[i].x1, pbox[i].y1,
-			  pbox[i].x2, pbox[i].y2);
-
-		BEGIN_LP_RING( 6 );
-		OUT_RING( BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4 );
-		OUT_RING( pitch | (0xCC << 16));
-		OUT_RING( (h << 16) | (w * cpp));
-		OUT_RING( dst );
-		OUT_RING( pitch );
-		OUT_RING( start );
-		ADVANCE_LP_RING();
-	}
-}
-
-
-static void i810_dma_dispatch_vertex(drm_device_t *dev,
-				     drm_buf_t *buf,
-				     int discard,
-				     int used)
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-   	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
-   	drm_clip_rect_t *box = sarea_priv->boxes;
-   	int nbox = sarea_priv->nbox;
-	unsigned long address = (unsigned long)buf->bus_address;
-	unsigned long start = address - dev->agp->base;
-	int i = 0;
-	char failed;
-   	RING_LOCALS;
-
-   	i810_kernel_lost_context(dev);
-
-   	if (nbox > I810_NR_SAREA_CLIPRECTS)
-		nbox = I810_NR_SAREA_CLIPRECTS;
-
-	if (discard) {
-		_DRM_CAS(buf_priv->in_use, I810_BUF_CLIENT,
-			    I810_BUF_HARDWARE, failed);
-		if (failed)
-			DRM_DEBUG("xxxx 2\n");
-	}
-
-	if (used > 4*1024)
-		used = 0;
-
-	if (sarea_priv->dirty)
-	   i810EmitState( dev );
-
-  	DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
-		  address, used, nbox);
-
-   	dev_priv->counter++;
-   	DRM_DEBUG(  "dispatch counter : %ld\n", dev_priv->counter);
-   	DRM_DEBUG(  "i810_dma_dispatch\n");
-   	DRM_DEBUG(  "start : %lx\n", start);
-	DRM_DEBUG(  "used : %d\n", used);
-   	DRM_DEBUG(  "start + used - 4 : %ld\n", start + used - 4);
-
-	if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
-		*(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE |
-					     sarea_priv->vertex_prim |
-					     ((used/4)-2));
-
-		if (used & 4) {
-			*(u32 *)((u32)buf_priv->virtual + used) = 0;
-			used += 4;
-		}
-
-		i810_unmap_buffer(buf);
-	}
-
-	if (used) {
-		do {
-			if (i < nbox) {
-				BEGIN_LP_RING(4);
-				OUT_RING( GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
-					  SC_ENABLE );
-				OUT_RING( GFX_OP_SCISSOR_INFO );
-				OUT_RING( box[i].x1 | (box[i].y1<<16) );
-				OUT_RING( (box[i].x2-1) | ((box[i].y2-1)<<16) );
-				ADVANCE_LP_RING();
-			}
-
-			BEGIN_LP_RING(4);
-			OUT_RING( CMD_OP_BATCH_BUFFER );
-			OUT_RING( start | BB1_PROTECTED );
-			OUT_RING( start + used - 4 );
-			OUT_RING( 0 );
-			ADVANCE_LP_RING();
-
-		} while (++i < nbox);
-	}
-
-	BEGIN_LP_RING(10);
-	OUT_RING( CMD_STORE_DWORD_IDX );
-	OUT_RING( 20 );
-	OUT_RING( dev_priv->counter );
-	OUT_RING( 0 );
-
-	if (discard) {
-		OUT_RING( CMD_STORE_DWORD_IDX );
-		OUT_RING( buf_priv->my_use_idx );
-		OUT_RING( I810_BUF_FREE );
-		OUT_RING( 0 );
-	}
-
-      	OUT_RING( CMD_REPORT_HEAD );
-	OUT_RING( 0 );
-   	ADVANCE_LP_RING();
-}
-
-
-/* Interrupts are only for flushing */
-void i810_dma_service(int irq, void *device, struct pt_regs *regs)
-{
-	drm_device_t	 *dev = (drm_device_t *)device;
-      	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-   	u16 temp;
-
-	atomic_inc(&dev->counts[_DRM_STAT_IRQ]);
-      	temp = I810_READ16(I810REG_INT_IDENTITY_R);
-   	temp = temp & ~(0x6000);
-   	if(temp != 0) I810_WRITE16(I810REG_INT_IDENTITY_R,
-				   temp); /* Clear all interrupts */
-	else
-	   return;
-
-   	queue_task(&dev->tq, &tq_immediate);
-   	mark_bh(IMMEDIATE_BH);
-}
-
-void i810_dma_immediate_bh(void *device)
-{
-	drm_device_t *dev = (drm_device_t *) device;
-      	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-
-   	atomic_set(&dev_priv->flush_done, 1);
-   	DRM_OS_WAKEUP_INT(&dev_priv->flush_queue);
-}
-
-static inline void i810_dma_emit_flush(drm_device_t *dev)
-{
-   	drm_i810_private_t *dev_priv = dev->dev_private;
-   	RING_LOCALS;
-
-   	i810_kernel_lost_context(dev);
-
-   	BEGIN_LP_RING(2);
-      	OUT_RING( CMD_REPORT_HEAD );
-      	OUT_RING( GFX_OP_USER_INTERRUPT );
-      	ADVANCE_LP_RING();
-
-/*  	i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */
-/*     	atomic_set(&dev_priv->flush_done, 1); */
-/*     	DRM_OS_WAKEUP_INT(&dev_priv->flush_queue); */
-}
-
-static inline void i810_dma_quiescent_emit(drm_device_t *dev)
-{
-      	drm_i810_private_t *dev_priv = dev->dev_private;
-   	RING_LOCALS;
-
-  	i810_kernel_lost_context(dev);
-
-   	BEGIN_LP_RING(4);
-   	OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
-   	OUT_RING( CMD_REPORT_HEAD );
-      	OUT_RING( 0 );
-      	OUT_RING( GFX_OP_USER_INTERRUPT );
-   	ADVANCE_LP_RING();
-
-/*  	i810_wait_ring( dev, dev_priv->ring.Size - 8 ); */
-/*     	atomic_set(&dev_priv->flush_done, 1); */
-/*     	DRM_OS_WAKEUP_INT(&dev_priv->flush_queue); */
-}
-
-void i810_dma_quiescent(drm_device_t *dev)
-{
-      	DECLARE_WAITQUEUE(entry, current);
-  	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-	unsigned long end;
-
-   	if(dev_priv == NULL) {
-	   	return;
-	}
-      	atomic_set(&dev_priv->flush_done, 0);
-   	add_wait_queue(&dev_priv->flush_queue, &entry);
-   	end = jiffies + (HZ*3);
-
-   	for (;;) {
-		current->state = TASK_INTERRUPTIBLE;
-	      	i810_dma_quiescent_emit(dev);
-	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("lockup\n");
-		   	break;
-		}
-	      	schedule_timeout(HZ*3);
-	      	if (signal_pending(current)) {
-		   	break;
-		}
-	}
-
-   	current->state = TASK_RUNNING;
-   	remove_wait_queue(&dev_priv->flush_queue, &entry);
-
-   	return;
-}
-
-static int i810_flush_queue(drm_device_t *dev)
-{
-   	DECLARE_WAITQUEUE(entry, current);
-  	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	unsigned long end;
-   	int i, ret = 0;
-
-   	if(dev_priv == NULL) {
-	   	return 0;
-	}
-      	atomic_set(&dev_priv->flush_done, 0);
-   	add_wait_queue(&dev_priv->flush_queue, &entry);
-   	end = jiffies + (HZ*3);
-   	for (;;) {
-		current->state = TASK_INTERRUPTIBLE;
-	      	i810_dma_emit_flush(dev);
-	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("lockup\n");
-		   	break;
-		}
-	      	schedule_timeout(HZ*3);
-	      	if (signal_pending(current)) {
-		   	ret = -EINTR; /* Can't restart */
-		   	break;
-		}
-	}
-
-   	current->state = TASK_RUNNING;
-   	remove_wait_queue(&dev_priv->flush_queue, &entry);
-
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-
-		char failed;
-		_DRM_CAS(buf_priv->in_use, I810_BUF_HARDWARE,
-				   I810_BUF_FREE, failed);
-
-		if (!failed)
-			DRM_DEBUG("reclaimed from HARDWARE\n");
-		if (used == I810_BUF_CLIENT)
-			DRM_DEBUG("still on client HARDWARE\n");
-	}
-
-   	return ret;
-}
-
-/* Must be called with the lock held */
-void i810_reclaim_buffers(drm_device_t *dev, pid_t pid)
-{
-	drm_device_dma_t *dma = dev->dma;
-	int		 i;
-
-	if (!dma) return;
-      	if (!dev->dev_private) return;
-	if (!dma->buflist) return;
-
-        i810_flush_queue(dev);
-
-	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
-
-		if (buf->pid == pid && buf_priv) {
-			char failed;
-			_DRM_CAS(buf_priv->in_use, I810_BUF_CLIENT,
-					   I810_BUF_FREE, failed);
-
-			if (!failed)
-	
-				DRM_DEBUG("reclaimed from client\n");
-		   	if(buf_priv->currently_mapped == I810_BUF_MAPPED)
-		     		buf_priv->currently_mapped = I810_BUF_UNMAPPED;
-		}
-	}
-}
-
-int i810_flush_ioctl( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-
-   	DRM_DEBUG("i810_flush_ioctl\n");
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_flush_ioctl called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
-   	i810_flush_queue(dev);
-   	return 0;
-}
-
-
-int i810_dma_vertex( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
-     					dev_priv->sarea_priv;
-	drm_i810_vertex_t vertex;
-
-	DRM_OS_KRNFROMUSR( vertex, (drm_i810_vertex_t *) data, sizeof(vertex) );
-
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_dma_vertex called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
-		  vertex.idx, vertex.used, vertex.discard);
-
-	if(vertex.idx < 0 || vertex.idx > dma->buf_count) DRM_OS_RETURN(EINVAL);
-
-	i810_dma_dispatch_vertex( dev,
-				  dma->buflist[ vertex.idx ],
-				  vertex.discard, vertex.used );
-
-   	atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]);
-	atomic_inc(&dev->counts[_DRM_STAT_DMA]);
-	sarea_priv->last_enqueue = dev_priv->counter-1;
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-
-	return 0;
-}
-
-
-
-int i810_clear_bufs( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-	drm_i810_clear_t clear;
-
-   	DRM_OS_KRNFROMUSR( clear, (drm_i810_clear_t *) data, sizeof(clear) );
-
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_clear_bufs called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
- 	/* GH: Someone's doing nasty things... */
- 	if (!dev->dev_private) {
- 		DRM_OS_RETURN(EINVAL);
- 	}
-
-	i810_dma_dispatch_clear( dev, clear.flags,
-				 clear.clear_color,
-				 clear.clear_depth );
-   	return 0;
-}
-
-int i810_swap_bufs( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-
-	DRM_DEBUG("i810_swap_bufs\n");
-
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_swap_buf called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	i810_dma_dispatch_swap( dev );
-   	return 0;
-}
-
-int i810_getage( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
-     					dev_priv->sarea_priv;
-
-      	sarea_priv->last_dispatch = (int) hw_status[5];
-	return 0;
-}
-
-int i810_getbuf( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-	int		  retcode   = 0;
-	drm_i810_dma_t	  d;
-   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
-     					dev_priv->sarea_priv;
-
-	DRM_DEBUG("getbuf\n");
-   	DRM_OS_KRNFROMUSR( d, (drm_i810_dma_t *) data, sizeof(d) );
-
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_dma called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	d.granted = 0;
-
-	retcode = i810_dma_get_buffer(dev, &d, filp);
-
-	DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
-		  DRM_OS_CURRENTPID, retcode, d.granted);
-
-	DRM_OS_KRNTOUSR( (drm_dma_t *) data, d, sizeof(d) );
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-
-	DRM_OS_RETURN(retcode);
-}
-
-int i810_copybuf( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_i810_copy_t	  d;
-   	drm_i810_private_t *dev_priv = (drm_i810_private_t *)dev->dev_private;
-   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
-     					dev_priv->sarea_priv;
-	drm_buf_t *buf;
-	drm_i810_buf_priv_t *buf_priv;
-	drm_device_dma_t *dma = dev->dma;
-
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i810_dma called without lock held\n");
-		DRM_OS_RETURN( EINVAL );
-	}
-
-   	DRM_OS_KRNFROMUSR( d, (drm_i810_copy_t *) data, sizeof(d) );
-
-        if(d.idx < 0 || d.idx > dma->buf_count) DRM_OS_RETURN(EINVAL);
-	buf = dma->buflist[ d.idx ];
-   	buf_priv = buf->dev_private;
-	if (buf_priv->currently_mapped != I810_BUF_MAPPED) DRM_OS_RETURN(EPERM);
-	if(d.used < 0 || d.used > buf->total) DRM_OS_RETURN(EINVAL);
-
-   	if (DRM_OS_COPYFROMUSR(buf_priv->virtual, d.address, d.used))
-		DRM_OS_RETURN( EFAULT );
-
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-
-	return 0;
-}
-
-int i810_docopy( DRM_OS_IOCTL )
-{
-	if(VM_DONTCOPY == 0) return 1;
-	return 0;
-}
diff --git a/bsd/i810/i810_drv.c b/bsd/i810/i810_drv.c
deleted file mode 100644
index e76e3a8a..00000000
--- a/bsd/i810/i810_drv.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/* i810_drv.c -- I810 driver -*- linux-c -*-
- * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-
-#include <sys/types.h>
-#include <sys/bus.h>
-#include <pci/pcivar.h>
-#include <opt_drm_linux.h>
-
-#include "i810.h"
-#include "drmP.h"
-#include "drm.h"
-#include "i810_drm.h"
-#include "i810_drv.h"
-
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"i810"
-#define DRIVER_DESC		"Intel i810"
-#define DRIVER_DATE		"20010616"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-
-/* Device IDs unknown.  Can someone help?  anholt@teleport.com */
-drm_chipinfo_t DRM(devicelist)[] = {
-	{0, 0, 0, NULL}
-};
-
-#define DRIVER_IOCTLS							    \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_INIT)]   = { i810_dma_init,    1, 1 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_VERTEX)] = { i810_dma_vertex,  1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_CLEAR)]  = { i810_clear_bufs,  1, 0 }, \
-      	[DRM_IOCTL_NR(DRM_IOCTL_I810_FLUSH)]  = { i810_flush_ioctl, 1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETAGE)] = { i810_getage,      1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I810_GETBUF)] = { i810_getbuf,      1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_SWAP)]   = { i810_swap_bufs,   1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_COPY)]   = { i810_copybuf,     1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I810_DOCOPY)] = { i810_docopy,      1, 0 },
-
-
-#define __HAVE_COUNTERS         4
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#define __HAVE_COUNTER9         _DRM_STAT_DMA
-
-
-#include "drm_agpsupport.h"
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lock.h"
-#include "drm_lists.h"
-#include "drm_memory.h"
-#include "drm_vm.h"
-#include "drm_sysctl.h"
-
-DRIVER_MODULE(i810, pci, i810_driver, i810_devclass, 0, 0);
diff --git a/bsd/i830/i830_dma.c b/bsd/i830/i830_dma.c
deleted file mode 100644
index fbdc9523..00000000
--- a/bsd/i830/i830_dma.c
+++ /dev/null
@@ -1,1420 +0,0 @@
-/* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- * 
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
- *	    Jeff Hartmann <jhartmann@valinux.com>
- *      Keith Whitwell <keithw@valinux.com>
- *      Abraham vd Merwe <abraham@2d3d.co.za>
- *
- */
-
-#define __NO_VERSION__
-#include "i830.h"
-#include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
-#include "i830_drv.h"
-#include <linux/interrupt.h>	/* For task queue support */
-
-/* in case we don't have a 2.3.99-pre6 kernel or later: */
-#ifndef VM_DONTCOPY
-#define VM_DONTCOPY 0
-#endif
-
-#define I830_BUF_FREE		2
-#define I830_BUF_CLIENT		1
-#define I830_BUF_HARDWARE      	0
-
-#define I830_BUF_UNMAPPED 0
-#define I830_BUF_MAPPED   1
-
-#define RING_LOCALS	unsigned int outring, ringmask; volatile char *virt;
-
-
-#define DO_IDLE_WORKAROUND()					\
-do {								\
-   int _head;							\
-   int _tail;							\
-   int _i;							\
-   do { 							\
-      _head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;	\
-      _tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;	\
-      for(_i = 0; _i < 65535; _i++);				\
-   } while(_head != _tail);					\
-} while(0)
-
-#define I830_SYNC_WORKAROUND 0
-
-#define BEGIN_LP_RING(n) do {				\
-	if (I830_VERBOSE)				\
-		DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",	\
-			  n, __FUNCTION__);		\
-	if (I830_SYNC_WORKAROUND)			\
-		DO_IDLE_WORKAROUND();			\
-	if (dev_priv->ring.space < n*4) 		\
-		i830_wait_ring(dev, n*4);		\
-	dev_priv->ring.space -= n*4;			\
-	outring = dev_priv->ring.tail;			\
-	ringmask = dev_priv->ring.tail_mask;		\
-	virt = dev_priv->ring.virtual_start;		\
-} while (0)
-
-#define ADVANCE_LP_RING() do {					\
-	if (I830_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n");	\
-	dev_priv->ring.tail = outring;				\
-	I830_WRITE(LP_RING + RING_TAIL, outring);		\
-} while(0)
-
-#define OUT_RING(n) do {						\
-	if (I830_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));	\
-	*(volatile unsigned int *)(virt + outring) = n;			\
-	outring += 4;							\
-	outring &= ringmask;						\
-} while (0)
-
-static inline void i830_print_status_page(drm_device_t *dev)
-{
-   	drm_device_dma_t *dma = dev->dma;
-      	drm_i830_private_t *dev_priv = dev->dev_private;
-	u32 *temp = (u32 *)dev_priv->hw_status_page;
-   	int i;
-
-   	DRM_DEBUG(  "hw_status: Interrupt Status : %x\n", temp[0]);
-   	DRM_DEBUG(  "hw_status: LpRing Head ptr : %x\n", temp[1]);
-   	DRM_DEBUG(  "hw_status: IRing Head ptr : %x\n", temp[2]);
-      	DRM_DEBUG(  "hw_status: Reserved : %x\n", temp[3]);
-   	DRM_DEBUG(  "hw_status: Driver Counter : %d\n", temp[5]);
-   	for(i = 9; i < dma->buf_count + 9; i++) {
-	   	DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 9, temp[i]);
-	}
-}
-
-static drm_buf_t *i830_freelist_get(drm_device_t *dev)
-{
-   	drm_device_dma_t *dma = dev->dma;
-	int		 i;
-   	int 		 used;
-   
-	/* Linear search might not be the best solution */
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-		/* In use is already a pointer */
-	   	used = cmpxchg(buf_priv->in_use, I830_BUF_FREE, 
-			       I830_BUF_CLIENT);
-	   	if(used == I830_BUF_FREE) {
-			return buf;
-		}
-	}
-   	return NULL;
-}
-
-/* This should only be called if the buffer is not sent to the hardware
- * yet, the hardware updates in use for us once its on the ring buffer.
- */
-
-static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf)
-{
-   	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-   	int used;
-   
-   	/* In use is already a pointer */
-   	used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
-   	if(used != I830_BUF_CLIENT) {
-	   	DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
-	   	return -EINVAL;
-	}
-   
-   	return 0;
-}
-
-static struct file_operations i830_buffer_fops = {
-	open:	 DRM(open),
-	flush:	 DRM(flush),
-	release: DRM(release),
-	ioctl:	 DRM(ioctl),
-	mmap:	 i830_mmap_buffers,
-	read:	 DRM(read),
-	fasync:	 DRM(fasync),
-      	poll:	 DRM(poll),
-};
-
-int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
-{
-	drm_file_t	    *priv	  = filp->private_data;
-	drm_device_t	    *dev;
-	drm_i830_private_t  *dev_priv;
-	drm_buf_t           *buf;
-	drm_i830_buf_priv_t *buf_priv;
-
-	lock_kernel();
-	dev	 = priv->dev;
-	dev_priv = dev->dev_private;
-	buf      = dev_priv->mmap_buffer;
-	buf_priv = buf->dev_private;
-   
-	vma->vm_flags |= (VM_IO | VM_DONTCOPY);
-	vma->vm_file = filp;
-   
-   	buf_priv->currently_mapped = I830_BUF_MAPPED;
-	unlock_kernel();
-
-	if (remap_page_range(vma->vm_start,
-			     VM_OFFSET(vma),
-			     vma->vm_end - vma->vm_start,
-			     vma->vm_page_prot)) return -EAGAIN;
-	return 0;
-}
-
-static int i830_map_buffer(drm_buf_t *buf, struct file *filp)
-{
-	drm_file_t	  *priv	  = filp->private_data;
-	drm_device_t	  *dev	  = priv->dev;
-	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-      	drm_i830_private_t *dev_priv = dev->dev_private;
-   	struct file_operations *old_fops;
-	int retcode = 0;
-
-	if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL;
-
-	if(VM_DONTCOPY != 0) {
-#if LINUX_VERSION_CODE <= 0x020402
-		down( &current->mm->mmap_sem );
-#else
-		down_write( &current->mm->mmap_sem );
-#endif
-		old_fops = filp->f_op;
-		filp->f_op = &i830_buffer_fops;
-		dev_priv->mmap_buffer = buf;
-		buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, 
-						    PROT_READ|PROT_WRITE,
-						    MAP_SHARED, 
-						    buf->bus_address);
-		dev_priv->mmap_buffer = NULL;
-   		filp->f_op = old_fops;
-		if ((unsigned long)buf_priv->virtual > -1024UL) {
-			/* Real error */
-			DRM_DEBUG("mmap error\n");
-			retcode = (signed int)buf_priv->virtual;
-			buf_priv->virtual = 0;
-		}
-#if LINUX_VERSION_CODE <= 0x020402
-		up( &current->mm->mmap_sem );
-#else
-		up_write( &current->mm->mmap_sem );
-#endif
-	} else {
-		buf_priv->virtual = buf_priv->kernel_virtual;
-   		buf_priv->currently_mapped = I830_BUF_MAPPED;
-	}
-	return retcode;
-}
-
-static int i830_unmap_buffer(drm_buf_t *buf)
-{
-	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-	int retcode = 0;
-
-	if(VM_DONTCOPY != 0) {
-		if(buf_priv->currently_mapped != I830_BUF_MAPPED) 
-			return -EINVAL;
-#if LINUX_VERSION_CODE <= 0x020402
-		down( &current->mm->mmap_sem );
-#else
-		down_write( &current->mm->mmap_sem );
-#endif
-#if LINUX_VERSION_CODE < 0x020399
-        	retcode = do_munmap((unsigned long)buf_priv->virtual, 
-				    (size_t) buf->total);
-#else
-        	retcode = do_munmap(current->mm, 
-				    (unsigned long)buf_priv->virtual, 
-				    (size_t) buf->total);
-#endif
-#if LINUX_VERSION_CODE <= 0x020402
-		up( &current->mm->mmap_sem );
-#else
-   		up_write( &current->mm->mmap_sem );
-#endif
-	}
-   	buf_priv->currently_mapped = I830_BUF_UNMAPPED;
-   	buf_priv->virtual = 0;
-
-	return retcode;
-}
-
-static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d, 
-			       struct file *filp)
-{
-	drm_file_t	  *priv	  = filp->private_data;
-	drm_buf_t	  *buf;
-	drm_i830_buf_priv_t *buf_priv;
-	int retcode = 0;
-
-	buf = i830_freelist_get(dev);
-	if (!buf) {
-		retcode = -ENOMEM;
-	   	DRM_DEBUG("retcode=%d\n", retcode);
-		return retcode;
-	}
-   
-	retcode = i830_map_buffer(buf, filp);
-	if(retcode) {
-		i830_freelist_put(dev, buf);
-	   	DRM_DEBUG("mapbuf failed, retcode %d\n", retcode);
-		return retcode;
-	}
-	buf->pid     = priv->pid;
-	buf_priv = buf->dev_private;	
-	d->granted = 1;
-   	d->request_idx = buf->idx;
-   	d->request_size = buf->total;
-   	d->virtual = buf_priv->virtual;
-
-	return retcode;
-}
-
-static unsigned long i830_alloc_page(drm_device_t *dev)
-{
-	unsigned long address;
-   
-	address = __get_free_page(GFP_KERNEL);
-	if(address == 0UL) 
-		return 0;
-	
-	atomic_inc(&virt_to_page(address)->count);
-	set_bit(PG_locked, &virt_to_page(address)->flags);
-   
-	return address;
-}
-
-static void i830_free_page(drm_device_t *dev, unsigned long page)
-{
-	if(page == 0UL) 
-		return;
-	
-	atomic_dec(&virt_to_page(page)->count);
-	clear_bit(PG_locked, &virt_to_page(page)->flags);
-	wake_up(&virt_to_page(page)->wait);
-	free_page(page);
-	return;
-}
-
-static int i830_dma_cleanup(drm_device_t *dev)
-{
-	drm_device_dma_t *dma = dev->dma;
-
-	if(dev->dev_private) {
-		int i;
-	   	drm_i830_private_t *dev_priv = 
-	     		(drm_i830_private_t *) dev->dev_private;
-	   
-	   	if(dev_priv->ring.virtual_start) {
-		   	DRM(ioremapfree)((void *) dev_priv->ring.virtual_start,
-					 dev_priv->ring.Size);
-		}
-	   	if(dev_priv->hw_status_page != 0UL) {
-		   	i830_free_page(dev, dev_priv->hw_status_page);
-		   	/* Need to rewrite hardware status page */
-		   	I830_WRITE(0x02080, 0x1ffff000);
-		}
-	   	DRM(free)(dev->dev_private, sizeof(drm_i830_private_t), 
-			 DRM_MEM_DRIVER);
-	   	dev->dev_private = NULL;
-
-		for (i = 0; i < dma->buf_count; i++) {
-			drm_buf_t *buf = dma->buflist[ i ];
-			drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-			DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total);
-		}
-	}
-   	return 0;
-}
-
-static int i830_wait_ring(drm_device_t *dev, int n)
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-   	drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
-   	int iters = 0;
-   	unsigned long end;
-	unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-
-	end = jiffies + (HZ*3);
-   	while (ring->space < n) {
-	   	int i;
-	
-	   	ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-	   	ring->space = ring->head - (ring->tail+8);
-		if (ring->space < 0) ring->space += ring->Size;
-	   
-		if (ring->head != last_head) {
-			end = jiffies + (HZ*3);
-			last_head = ring->head;
-		}
-	  
-	   	iters++;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("space: %d wanted %d\n", ring->space, n);
-		   	DRM_ERROR("lockup\n");
-		   	goto out_wait_ring;
-		}
-
-	   	for (i = 0 ; i < 2000 ; i++) ;
-	}
-
-out_wait_ring:   
-   	return iters;
-}
-
-static void i830_kernel_lost_context(drm_device_t *dev)
-{
-      	drm_i830_private_t *dev_priv = dev->dev_private;
-   	drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
-      
-   	ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
-     	ring->tail = I830_READ(LP_RING + RING_TAIL);
-     	ring->space = ring->head - (ring->tail+8);
-     	if (ring->space < 0) ring->space += ring->Size;
-}
-
-static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv)
-{
-      	drm_device_dma_t *dma = dev->dma;
-   	int my_idx = 36;
-   	u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
-   	int i;
-
-   	if(dma->buf_count > 1019) {
-	   	/* Not enough space in the status page for the freelist */
-	   	return -EINVAL;
-	}
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-
-	   	buf_priv->in_use = hw_status++;
-	   	buf_priv->my_use_idx = my_idx;
-	   	my_idx += 4;
-
-	   	*buf_priv->in_use = I830_BUF_FREE;
-
-		buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address, 
-							buf->total);
-	}
-	return 0;
-}
-
-static int i830_dma_initialize(drm_device_t *dev, 
-			       drm_i830_private_t *dev_priv,
-			       drm_i830_init_t *init)
-{
-	struct list_head *list;
-
-   	memset(dev_priv, 0, sizeof(drm_i830_private_t));
-
-	list_for_each(list, &dev->maplist->head) {
-		drm_map_list_t *r_list = (drm_map_list_t *)list;
-		if( r_list->map &&
-		    r_list->map->type == _DRM_SHM &&
-		    r_list->map->flags & _DRM_CONTAINS_LOCK ) {
-			dev_priv->sarea_map = r_list->map;
- 			break;
- 		}
- 	}
-
-	if(!dev_priv->sarea_map) {
-		dev->dev_private = (void *)dev_priv;
-		i830_dma_cleanup(dev);
-		DRM_ERROR("can not find sarea!\n");
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->mmio_map, init->mmio_offset );
-	if(!dev_priv->mmio_map) {
-		dev->dev_private = (void *)dev_priv;
-		i830_dma_cleanup(dev);
-		DRM_ERROR("can not find mmio map!\n");
-		return -EINVAL;
-	}
-	DRM_FIND_MAP( dev_priv->buffer_map, init->buffers_offset );
-	if(!dev_priv->buffer_map) {
-		dev->dev_private = (void *)dev_priv;
-		i830_dma_cleanup(dev);
-		DRM_ERROR("can not find dma buffer map!\n");
-		return -EINVAL;
-	}
-
-	dev_priv->sarea_priv = (drm_i830_sarea_t *)
-		((u8 *)dev_priv->sarea_map->handle +
-		 init->sarea_priv_offset);
-
-   	atomic_set(&dev_priv->flush_done, 0);
-	init_waitqueue_head(&dev_priv->flush_queue);
-
-   	dev_priv->ring.Start = init->ring_start;
-   	dev_priv->ring.End = init->ring_end;
-   	dev_priv->ring.Size = init->ring_size;
-
-   	dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base + 
-						    init->ring_start, 
-						    init->ring_size);
-
-   	if (dev_priv->ring.virtual_start == NULL) {
-		dev->dev_private = (void *) dev_priv;
-	   	i830_dma_cleanup(dev);
-	   	DRM_ERROR("can not ioremap virtual address for"
-			  " ring buffer\n");
-	   	return -ENOMEM;
-	}
-
-   	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
-   
-	dev_priv->w = init->w;
-	dev_priv->h = init->h;
-	dev_priv->pitch = init->pitch;
-	dev_priv->back_offset = init->back_offset;
-	dev_priv->depth_offset = init->depth_offset;
-
-	dev_priv->front_di1 = init->front_offset | init->pitch_bits;
-	dev_priv->back_di1 = init->back_offset | init->pitch_bits;
-	dev_priv->zi1 = init->depth_offset | init->pitch_bits;
-
-	dev_priv->cpp = init->cpp;
-	/* We are using seperate values as placeholders for mechanisms for
-	 * private backbuffer/depthbuffer usage.
-	 */
-
-	dev_priv->back_pitch = init->back_pitch;
-	dev_priv->depth_pitch = init->depth_pitch;
-
-   	/* Program Hardware Status Page */
-   	dev_priv->hw_status_page = i830_alloc_page(dev);
-   	if(dev_priv->hw_status_page == 0UL) {
-		dev->dev_private = (void *)dev_priv;
-		i830_dma_cleanup(dev);
-		DRM_ERROR("Can not allocate hardware status page\n");
-		return -ENOMEM;
-	}
-   	memset((void *) dev_priv->hw_status_page, 0, PAGE_SIZE);
-	DRM_DEBUG("hw status page @ %lx\n", dev_priv->hw_status_page);
-   
-   	I830_WRITE(0x02080, virt_to_bus((void *)dev_priv->hw_status_page));
-	DRM_DEBUG("Enabled hardware status page\n");
-   
-   	/* Now we need to init our freelist */
-   	if(i830_freelist_init(dev, dev_priv) != 0) {
-		dev->dev_private = (void *)dev_priv;
-	   	i830_dma_cleanup(dev);
-	   	DRM_ERROR("Not enough space in the status page for"
-			  " the freelist\n");
-	   	return -ENOMEM;
-	}
-	dev->dev_private = (void *)dev_priv;
-
-   	return 0;
-}
-
-int i830_dma_init(struct inode *inode, struct file *filp,
-		  unsigned int cmd, unsigned long arg)
-{
-   	drm_file_t *priv = filp->private_data;
-   	drm_device_t *dev = priv->dev;
-   	drm_i830_private_t *dev_priv;
-   	drm_i830_init_t init;
-   	int retcode = 0;
-	
-  	if (copy_from_user(&init, (drm_i830_init_t *)arg, sizeof(init)))
-		return -EFAULT;
-	
-   	switch(init.func) {
-	 	case I830_INIT_DMA:
-			dev_priv = DRM(alloc)(sizeof(drm_i830_private_t), 
-					      DRM_MEM_DRIVER);
-	   		if(dev_priv == NULL) return -ENOMEM;
-	   		retcode = i830_dma_initialize(dev, dev_priv, &init);
-	   	break;
-	 	case I830_CLEANUP_DMA:
-	   		retcode = i830_dma_cleanup(dev);
-	   	break;
-	 	default:
-	   		retcode = -EINVAL;
-	   	break;
-	}
-   
-   	return retcode;
-}
-
-/* Most efficient way to verify state for the i830 is as it is
- * emitted.  Non-conformant state is silently dropped.
- *
- * Use 'volatile' & local var tmp to force the emitted values to be
- * identical to the verified ones.
- */
-static void i830EmitContextVerified( drm_device_t *dev, 
-				     volatile unsigned int *code )
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	int i, j = 0;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I830_CTX_SETUP_SIZE );
-	for ( i = 0 ; i < I830_CTX_SETUP_SIZE ; i++ ) {
-		tmp = code[i];
-
-#if 0
-		if ((tmp & (7<<29)) == (3<<29) &&
-		    (tmp & (0x1f<<24)) < (0x1d<<24)) {
-			OUT_RING( tmp ); 
-			j++;
-		} else {
-			printk("Skipping %d\n", i);
-		}
-#else
-		OUT_RING( tmp ); 
-		j++;
-#endif
-	}
-
-	if (j & 1) 
-		OUT_RING( 0 ); 
-
-	ADVANCE_LP_RING();
-}
-
-static void i830EmitTexVerified( drm_device_t *dev, 
-				 volatile unsigned int *code ) 
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	int i, j = 0;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I830_TEX_SETUP_SIZE );
-
-	OUT_RING( GFX_OP_MAP_INFO );
-	OUT_RING( code[I830_TEXREG_MI1] );
-	OUT_RING( code[I830_TEXREG_MI2] );
-	OUT_RING( code[I830_TEXREG_MI3] );
-	OUT_RING( code[I830_TEXREG_MI4] );
-	OUT_RING( code[I830_TEXREG_MI5] );
-
-	for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) {
-		tmp = code[i];
-		OUT_RING( tmp ); 
-		j++;
-	} 
-
-	if (j & 1) 
-		OUT_RING( 0 ); 
-
-	ADVANCE_LP_RING();
-}
-
-static void i830EmitTexBlendVerified( drm_device_t *dev, 
-				     volatile unsigned int *code,
-				     volatile unsigned int num)
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	int i, j = 0;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( num );
-
-	for ( i = 0 ; i < num ; i++ ) {
-		tmp = code[i];
-		OUT_RING( tmp );
-		j++;
-	}
-
-	if (j & 1) 
-		OUT_RING( 0 ); 
-
-	ADVANCE_LP_RING();
-}
-
-static void i830EmitTexPalette( drm_device_t *dev,
-			        unsigned int *palette,
-			        int number,
-			        int is_shared )
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	int i;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( 258 );
-
-	if(is_shared == 1) {
-		OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
-			 MAP_PALETTE_NUM(0) |
-			 MAP_PALETTE_BOTH);
-	} else {
-		OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
-	}
-	for(i = 0; i < 256; i++) {
-		OUT_RING(palette[i]);
-	}
-	OUT_RING(0);
-}
-
-/* Need to do some additional checking when setting the dest buffer.
- */
-static void i830EmitDestVerified( drm_device_t *dev, 
-				  volatile unsigned int *code ) 
-{	
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	unsigned int tmp;
-	RING_LOCALS;
-
-	BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 6 );
-
-	tmp = code[I830_DESTREG_CBUFADDR];
-	if (tmp == dev_priv->front_di1) {
-		/* Don't use fence when front buffer rendering */
-		OUT_RING( CMD_OP_DESTBUFFER_INFO );
-		OUT_RING( BUF_3D_ID_COLOR_BACK | 
-			  BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) );
-		OUT_RING( tmp );
-
-		OUT_RING( CMD_OP_DESTBUFFER_INFO );
-		OUT_RING( BUF_3D_ID_DEPTH |
-			  BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
-		OUT_RING( dev_priv->zi1 );
-	} else if(tmp == dev_priv->back_di1) {
-		OUT_RING( CMD_OP_DESTBUFFER_INFO );
-		OUT_RING( BUF_3D_ID_COLOR_BACK | 
-			  BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
-			  BUF_3D_USE_FENCE);
-		OUT_RING( tmp );
-
-		OUT_RING( CMD_OP_DESTBUFFER_INFO );
-		OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE | 
-			  BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
-		OUT_RING( dev_priv->zi1 );
-	} else {
-		DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
-			  tmp, dev_priv->front_di1, dev_priv->back_di1);
-	}
-
-	/* invarient:
-	 */
-
-
-	OUT_RING( GFX_OP_DESTBUFFER_VARS );
-	OUT_RING( code[I830_DESTREG_DV1] );
-
-	OUT_RING( GFX_OP_DRAWRECT_INFO );
-	OUT_RING( code[I830_DESTREG_DR1] );
-	OUT_RING( code[I830_DESTREG_DR2] );
-	OUT_RING( code[I830_DESTREG_DR3] );
-	OUT_RING( code[I830_DESTREG_DR4] );
-
-	/* Need to verify this */
-	tmp = code[I830_DESTREG_SENABLE];
-	if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
-		OUT_RING( tmp );
-	} else {
-		DRM_DEBUG("bad scissor enable\n");
-		OUT_RING( 0 );
-	}
-
-	OUT_RING( code[I830_DESTREG_SENABLE] );
-
-	OUT_RING( GFX_OP_SCISSOR_RECT );
-	OUT_RING( code[I830_DESTREG_SR1] );
-	OUT_RING( code[I830_DESTREG_SR2] );
-
-	ADVANCE_LP_RING();
-}
-
-static void i830EmitState( drm_device_t *dev )
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-      	drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	if (dirty & I830_UPLOAD_BUFFERS) {
-		i830EmitDestVerified( dev, sarea_priv->BufferState );
-		sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
-	}
-
-	if (dirty & I830_UPLOAD_CTX) {
-		i830EmitContextVerified( dev, sarea_priv->ContextState );
-		sarea_priv->dirty &= ~I830_UPLOAD_CTX;
-	}
-
-	if (dirty & I830_UPLOAD_TEX0) {
-		i830EmitTexVerified( dev, sarea_priv->TexState[0] );
-		sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
-	}
-
-	if (dirty & I830_UPLOAD_TEX1) {
-		i830EmitTexVerified( dev, sarea_priv->TexState[1] );
-		sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
-	}
-
-	if (dirty & I830_UPLOAD_TEXBLEND0) {
-		i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0],
-				sarea_priv->TexBlendStateWordsUsed[0]);
-		sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
-	}
-
-	if (dirty & I830_UPLOAD_TEXBLEND1) {
-		i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1],
-				sarea_priv->TexBlendStateWordsUsed[1]);
-		sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
-	}
-
-	if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
-	   i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
-	} else {
-	   if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
-	      i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
-	      sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
-	   }
-	   if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
-	      i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
-	      sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
-	   }
-	}
-}
-
-static void i830_dma_dispatch_clear( drm_device_t *dev, int flags, 
-				    unsigned int clear_color,
-				    unsigned int clear_zval,
-				    unsigned int clear_depthmask)
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-      	drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int pitch = dev_priv->pitch;
-	int cpp = dev_priv->cpp;
-	int i;
-	unsigned int BR13, CMD, D_CMD;
-	RING_LOCALS;
-
-  	i830_kernel_lost_context(dev);
-
-	switch(cpp) {
-	case 2: 
-		BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24);
-		D_CMD = CMD = XY_COLOR_BLT_CMD;
-		break;
-	case 4:
-		BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25);
-		CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | 
-		       XY_COLOR_BLT_WRITE_RGB);
-		D_CMD = XY_COLOR_BLT_CMD;
-		if(clear_depthmask & 0x00ffffff)
-			D_CMD |= XY_COLOR_BLT_WRITE_RGB;
-		if(clear_depthmask & 0xff000000)
-			D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
-		break;
-	default:
-		BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24);
-		D_CMD = CMD = XY_COLOR_BLT_CMD;
-		break;
-	}
-
-      	if (nbox > I830_NR_SAREA_CLIPRECTS)
-     		nbox = I830_NR_SAREA_CLIPRECTS;
-
-	for (i = 0 ; i < nbox ; i++, pbox++) {
-		if (pbox->x1 > pbox->x2 ||
-		    pbox->y1 > pbox->y2 ||
-		    pbox->x2 > dev_priv->w ||
-		    pbox->y2 > dev_priv->h)
-			continue;
-
-	   	if ( flags & I830_FRONT ) {	    
-		   	DRM_DEBUG("clear front\n");
-			BEGIN_LP_RING( 6 );	    
-			OUT_RING( CMD );
-			OUT_RING( BR13 );
-			OUT_RING( (pbox->y1 << 16) | pbox->x1 );
-			OUT_RING( (pbox->y2 << 16) | pbox->x2 );
-			OUT_RING( 0 );
-			OUT_RING( clear_color );
-			ADVANCE_LP_RING();
-		}
-
-		if ( flags & I830_BACK ) {
-			DRM_DEBUG("clear back\n");
-			BEGIN_LP_RING( 6 );	    
-			OUT_RING( CMD );
-			OUT_RING( BR13 );
-			OUT_RING( (pbox->y1 << 16) | pbox->x1 );
-			OUT_RING( (pbox->y2 << 16) | pbox->x2 );
-			OUT_RING( dev_priv->back_offset );
-			OUT_RING( clear_color );
-			ADVANCE_LP_RING();
-		}
-
-		if ( flags & I830_DEPTH ) {
-			DRM_DEBUG("clear depth\n");
-			BEGIN_LP_RING( 6 );
-			OUT_RING( D_CMD );
-			OUT_RING( BR13 );
-			OUT_RING( (pbox->y1 << 16) | pbox->x1 );
-			OUT_RING( (pbox->y2 << 16) | pbox->x2 );
-			OUT_RING( dev_priv->depth_offset );
-			OUT_RING( clear_zval );
-			ADVANCE_LP_RING();
-		}
-	}
-}
-
-static void i830_dma_dispatch_swap( drm_device_t *dev )
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-      	drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int pitch = dev_priv->pitch;
-	int cpp = dev_priv->cpp;
-	int ofs = dev_priv->back_offset;
-	int i;
-	unsigned int CMD, BR13;
-	RING_LOCALS;
-
-	DRM_DEBUG("swapbuffers\n");
-
-	switch(cpp) {
-	case 2: 
-		BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24);
-		CMD = XY_SRC_COPY_BLT_CMD;
-		break;
-	case 4:
-		BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25);
-		CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
-		       XY_SRC_COPY_BLT_WRITE_RGB);
-		break;
-	default:
-		BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24);
-		CMD = XY_SRC_COPY_BLT_CMD;
-		break;
-	}
-
-  	i830_kernel_lost_context(dev);
-
-      	if (nbox > I830_NR_SAREA_CLIPRECTS)
-     		nbox = I830_NR_SAREA_CLIPRECTS;
-
-	for (i = 0 ; i < nbox; i++, pbox++) 
-	{
-		if (pbox->x1 > pbox->x2 ||
-		    pbox->y1 > pbox->y2 ||
-		    pbox->x2 > dev_priv->w ||
-		    pbox->y2 > dev_priv->h)
-			continue;
- 
-		DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
-			  pbox->x1, pbox->y1,
-			  pbox->x2, pbox->y2);
-
-		BEGIN_LP_RING( 8 );
-		OUT_RING( CMD );
-		OUT_RING( BR13 );
-
-		OUT_RING( (pbox->y1 << 16) |
-			  pbox->x1 );
-		OUT_RING( (pbox->y2 << 16) |
-			  pbox->x2 );
-
-		OUT_RING( 0 /* front ofs always zero */ );
-		OUT_RING( (pbox->y1 << 16) |
-			  pbox->x1 );
-
-		OUT_RING( BR13 & 0xffff );
-		OUT_RING( ofs );
-
-		ADVANCE_LP_RING();
-	}
-}
-
-
-static void i830_dma_dispatch_vertex(drm_device_t *dev, 
-				     drm_buf_t *buf,
-				     int discard,
-				     int used)
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-   	drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
-   	drm_clip_rect_t *box = sarea_priv->boxes;
-   	int nbox = sarea_priv->nbox;
-	unsigned long address = (unsigned long)buf->bus_address;
-	unsigned long start = address - dev->agp->base;     
-	int i = 0, u;
-   	RING_LOCALS;
-
-   	i830_kernel_lost_context(dev);
-
-   	if (nbox > I830_NR_SAREA_CLIPRECTS) 
-		nbox = I830_NR_SAREA_CLIPRECTS;
-
-	if (discard) {
-		u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, 
-			    I830_BUF_HARDWARE);
-		if(u != I830_BUF_CLIENT) {
-			DRM_DEBUG("xxxx 2\n");
-		}
-	}
-
-	if (used > 4*1024) 
-		used = 0;
-
-	if (sarea_priv->dirty)
-	   i830EmitState( dev );
-
-  	DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n", 
-		  address, used, nbox);
-
-   	dev_priv->counter++;
-   	DRM_DEBUG(  "dispatch counter : %ld\n", dev_priv->counter);
-   	DRM_DEBUG(  "i830_dma_dispatch\n");
-   	DRM_DEBUG(  "start : %lx\n", start);
-	DRM_DEBUG(  "used : %d\n", used);
-   	DRM_DEBUG(  "start + used - 4 : %ld\n", start + used - 4);
-
-	if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
-		*(u32 *)buf_priv->virtual = (GFX_OP_PRIMITIVE |
-					     sarea_priv->vertex_prim |
-					     ((used/4)-2));
-		
-		if (used & 4) {
-			*(u32 *)((u32)buf_priv->virtual + used) = 0;
-			used += 4;
-		}
-
-		i830_unmap_buffer(buf);
-	}
-		   
-	if (used) {
-		do {
-			if (i < nbox) {
-				BEGIN_LP_RING(6);
-				OUT_RING( GFX_OP_DRAWRECT_INFO );
-				OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] );
-				OUT_RING( box[i].x1 | (box[i].y1<<16) );
-				OUT_RING( box[i].x2 | (box[i].y2<<16) );
-				OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] );
-				OUT_RING( 0 );
-				ADVANCE_LP_RING();
-			}
-
-			BEGIN_LP_RING(4);
-
-			OUT_RING( MI_BATCH_BUFFER );
-			OUT_RING( start | MI_BATCH_NON_SECURE );
-			OUT_RING( start + used - 4 );
-			OUT_RING( 0 );
-			ADVANCE_LP_RING();
-			
-		} while (++i < nbox);
-	}
-
-	BEGIN_LP_RING(10);
-	OUT_RING( CMD_STORE_DWORD_IDX );
-	OUT_RING( 20 );
-	OUT_RING( dev_priv->counter );
-	OUT_RING( 0 );
-
-	if (discard) {
-		OUT_RING( CMD_STORE_DWORD_IDX );
-		OUT_RING( buf_priv->my_use_idx );
-		OUT_RING( I830_BUF_FREE );
-		OUT_RING( 0 );
-	}
-
-      	OUT_RING( CMD_REPORT_HEAD );
-	OUT_RING( 0 );
-   	ADVANCE_LP_RING();
-}
-
-/* Interrupts are only for flushing */
-void i830_dma_service(int irq, void *device, struct pt_regs *regs)
-{
-	drm_device_t	 *dev = (drm_device_t *)device;
-      	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-   	u16 temp;
-   
-      	temp = I830_READ16(I830REG_INT_IDENTITY_R);
-   	temp = temp & ~(0x6000);
-   	if(temp != 0) I830_WRITE16(I830REG_INT_IDENTITY_R, 
-				   temp); /* Clear all interrupts */
-	else
-	   return;
- 
-   	queue_task(&dev->tq, &tq_immediate);
-   	mark_bh(IMMEDIATE_BH);
-}
-
-void DRM(dma_immediate_bh)(void *device)
-{
-	drm_device_t *dev = (drm_device_t *) device;
-      	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-
-   	atomic_set(&dev_priv->flush_done, 1);
-   	wake_up_interruptible(&dev_priv->flush_queue);
-}
-
-static inline void i830_dma_emit_flush(drm_device_t *dev)
-{
-   	drm_i830_private_t *dev_priv = dev->dev_private;
-   	RING_LOCALS;
-
-   	i830_kernel_lost_context(dev);
-
-   	BEGIN_LP_RING(2);
-      	OUT_RING( CMD_REPORT_HEAD );
-      	OUT_RING( GFX_OP_USER_INTERRUPT );
-      	ADVANCE_LP_RING();
-
-	i830_wait_ring( dev, dev_priv->ring.Size - 8 );
-	atomic_set(&dev_priv->flush_done, 1);
-	wake_up_interruptible(&dev_priv->flush_queue);
-}
-
-static inline void i830_dma_quiescent_emit(drm_device_t *dev)
-{
-      	drm_i830_private_t *dev_priv = dev->dev_private;
-   	RING_LOCALS;
-
-  	i830_kernel_lost_context(dev);
-
-   	BEGIN_LP_RING(4);
-   	OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
-   	OUT_RING( CMD_REPORT_HEAD );
-      	OUT_RING( 0 );
-      	OUT_RING( GFX_OP_USER_INTERRUPT );
-   	ADVANCE_LP_RING();
-
-	i830_wait_ring( dev, dev_priv->ring.Size - 8 );
-	atomic_set(&dev_priv->flush_done, 1);
-	wake_up_interruptible(&dev_priv->flush_queue);
-}
-
-void i830_dma_quiescent(drm_device_t *dev)
-{
-      	DECLARE_WAITQUEUE(entry, current);
-  	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-	unsigned long end;      
-
-   	if(dev_priv == NULL) {
-	   	return;
-	}
-      	atomic_set(&dev_priv->flush_done, 0);
-   	add_wait_queue(&dev_priv->flush_queue, &entry);
-   	end = jiffies + (HZ*3);
-   
-   	for (;;) {
-		current->state = TASK_INTERRUPTIBLE;
-	      	i830_dma_quiescent_emit(dev);
-	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("lockup\n");
-		   	break;
-		}	   
-	      	schedule_timeout(HZ*3);
-	      	if (signal_pending(current)) {
-		   	break;
-		}
-	}
-   
-   	current->state = TASK_RUNNING;
-   	remove_wait_queue(&dev_priv->flush_queue, &entry);
-   
-   	return;
-}
-
-static int i830_flush_queue(drm_device_t *dev)
-{
-   	DECLARE_WAITQUEUE(entry, current);
-  	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	unsigned long end;
-   	int i, ret = 0;      
-
-   	if(dev_priv == NULL) {
-	   	return 0;
-	}
-      	atomic_set(&dev_priv->flush_done, 0);
-   	add_wait_queue(&dev_priv->flush_queue, &entry);
-   	end = jiffies + (HZ*3);
-   	for (;;) {
-		current->state = TASK_INTERRUPTIBLE;
-	      	i830_dma_emit_flush(dev);
-	   	if (atomic_read(&dev_priv->flush_done) == 1) break;
-		if((signed)(end - jiffies) <= 0) {
-		   	DRM_ERROR("lockup\n");
-		   	break;
-		}	   
-	      	schedule_timeout(HZ*3);
-	      	if (signal_pending(current)) {
-		   	ret = -EINTR; /* Can't restart */
-		   	break;
-		}
-	}
-   
-   	current->state = TASK_RUNNING;
-   	remove_wait_queue(&dev_priv->flush_queue, &entry);
-
-
-   	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-	   
-		int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE, 
-				   I830_BUF_FREE);
-
-		if (used == I830_BUF_HARDWARE)
-			DRM_DEBUG("reclaimed from HARDWARE\n");
-		if (used == I830_BUF_CLIENT)
-			DRM_DEBUG("still on client HARDWARE\n");
-	}
-
-   	return ret;
-}
-
-/* Must be called with the lock held */
-void i830_reclaim_buffers(drm_device_t *dev, pid_t pid)
-{
-	drm_device_dma_t *dma = dev->dma;
-	int		 i;
-
-	if (!dma) return;
-      	if (!dev->dev_private) return;
-	if (!dma->buflist) return;
-
-        i830_flush_queue(dev);
-
-	for (i = 0; i < dma->buf_count; i++) {
-	   	drm_buf_t *buf = dma->buflist[ i ];
-	   	drm_i830_buf_priv_t *buf_priv = buf->dev_private;
-	   
-		if (buf->pid == pid && buf_priv) {
-			int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, 
-					   I830_BUF_FREE);
-
-			if (used == I830_BUF_CLIENT)
-				DRM_DEBUG("reclaimed from client\n");
-		   	if(buf_priv->currently_mapped == I830_BUF_MAPPED)
-		     		buf_priv->currently_mapped = I830_BUF_UNMAPPED;
-		}
-	}
-}
-
-int i830_flush_ioctl(struct inode *inode, struct file *filp, 
-		     unsigned int cmd, unsigned long arg)
-{
-   	drm_file_t	  *priv	  = filp->private_data;
-   	drm_device_t	  *dev	  = priv->dev;
-   
-   	DRM_DEBUG("i830_flush_ioctl\n");
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_flush_ioctl called without lock held\n");
-		return -EINVAL;
-	}
-
-   	i830_flush_queue(dev);
-   	return 0;
-}
-
-int i830_dma_vertex(struct inode *inode, struct file *filp,
-	       unsigned int cmd, unsigned long arg)
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_device_dma_t *dma = dev->dma;
-   	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 
-     					dev_priv->sarea_priv; 
-	drm_i830_vertex_t vertex;
-
-	if (copy_from_user(&vertex, (drm_i830_vertex_t *)arg, sizeof(vertex)))
-		return -EFAULT;
-
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_dma_vertex called without lock held\n");
-		return -EINVAL;
-	}
-
-	DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
-		  vertex.idx, vertex.used, vertex.discard);
-
-	if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
-
-	i830_dma_dispatch_vertex( dev, 
-				  dma->buflist[ vertex.idx ], 
-				  vertex.discard, vertex.used );
-
-	sarea_priv->last_enqueue = dev_priv->counter-1;
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-   
-	return 0;
-}
-
-int i830_clear_bufs(struct inode *inode, struct file *filp,
-		   unsigned int cmd, unsigned long arg)
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-	drm_i830_clear_t clear;
-
-   	if (copy_from_user(&clear, (drm_i830_clear_t *)arg, sizeof(clear)))
-		return -EFAULT;
-   
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_clear_bufs called without lock held\n");
-		return -EINVAL;
-	}
-
-	/* GH: Someone's doing nasty things... */
-	if (!dev->dev_private) {
-		return -EINVAL;
-	}
-
-	i830_dma_dispatch_clear( dev, clear.flags, 
-				 clear.clear_color, 
-				 clear.clear_depth,
-			         clear.clear_depthmask);
-   	return 0;
-}
-
-int i830_swap_bufs(struct inode *inode, struct file *filp,
-		  unsigned int cmd, unsigned long arg)
-{
-	drm_file_t *priv = filp->private_data;
-	drm_device_t *dev = priv->dev;
-   
-	DRM_DEBUG("i830_swap_bufs\n");
-
-   	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_swap_buf called without lock held\n");
-		return -EINVAL;
-	}
-
-	i830_dma_dispatch_swap( dev );
-   	return 0;
-}
-
-int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
-		unsigned long arg)
-{
-   	drm_file_t	  *priv	    = filp->private_data;
-	drm_device_t	  *dev	    = priv->dev;
-   	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-      	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 
-     					dev_priv->sarea_priv; 
-
-      	sarea_priv->last_dispatch = (int) hw_status[5];
-	return 0;
-}
-
-int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
-		unsigned long arg)
-{
-	drm_file_t	  *priv	    = filp->private_data;
-	drm_device_t	  *dev	    = priv->dev;
-	int		  retcode   = 0;
-	drm_i830_dma_t	  d;
-   	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 
-     					dev_priv->sarea_priv; 
-
-	DRM_DEBUG("getbuf\n");
-   	if (copy_from_user(&d, (drm_i830_dma_t *)arg, sizeof(d)))
-		return -EFAULT;
-   
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_dma called without lock held\n");
-		return -EINVAL;
-	}
-	
-	d.granted = 0;
-
-	retcode = i830_dma_get_buffer(dev, &d, filp);
-
-	DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
-		  current->pid, retcode, d.granted);
-
-	if (copy_to_user((drm_dma_t *)arg, &d, sizeof(d)))
-		return -EFAULT;
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-
-	return retcode;
-}
-
-int i830_copybuf(struct inode *inode, struct file *filp, unsigned int cmd,
-		unsigned long arg)
-{
-	drm_file_t	  *priv	    = filp->private_data;
-	drm_device_t	  *dev	    = priv->dev;
-	drm_i830_copy_t	  d;
-   	drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
-   	u32 *hw_status = (u32 *)dev_priv->hw_status_page;
-   	drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) 
-     					dev_priv->sarea_priv; 
-	drm_buf_t *buf;
-	drm_i830_buf_priv_t *buf_priv;
-	drm_device_dma_t *dma = dev->dma;
-
-	if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
-		DRM_ERROR("i830_dma called without lock held\n");
-		return -EINVAL;
-	}
-   
-   	if (copy_from_user(&d, (drm_i830_copy_t *)arg, sizeof(d)))
-		return -EFAULT;
-
-	if(d.idx < 0 || d.idx > dma->buf_count) return -EINVAL;
-	buf = dma->buflist[ d.idx ];
-   	buf_priv = buf->dev_private;
-	if (buf_priv->currently_mapped != I830_BUF_MAPPED) return -EPERM;
-
-	if(d.used < 0 || d.used > buf->total) return -EINVAL;
-
-   	if (copy_from_user(buf_priv->virtual, d.address, d.used))
-		return -EFAULT;
-
-   	sarea_priv->last_dispatch = (int) hw_status[5];
-
-	return 0;
-}
-
-int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
-		unsigned long arg)
-{
-	if(VM_DONTCOPY == 0) return 1;
-	return 0;
-}
diff --git a/bsd/i830/i830_drv.c b/bsd/i830/i830_drv.c
deleted file mode 100644
index ad31d1ef..00000000
--- a/bsd/i830/i830_drv.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* i830_drv.c -- I810 driver -*- linux-c -*-
- * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- *    Abraham vd Merwe <abraham@2d3d.co.za>
- */
-
-#include <linux/config.h>
-#include "i830.h"
-#include "drmP.h"
-#include "drm.h"
-#include "i830_drm.h"
-#include "i830_drv.h"
-
-#define DRIVER_AUTHOR		"VA Linux Systems Inc."
-
-#define DRIVER_NAME		"i830"
-#define DRIVER_DESC		"Intel 830M"
-#define DRIVER_DATE		"20011004"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-
-#define DRIVER_IOCTLS							    \
-	[DRM_IOCTL_NR(DRM_IOCTL_I830_INIT)]   = { i830_dma_init,    1, 1 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_VERTEX)] = { i830_dma_vertex,  1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_CLEAR)]  = { i830_clear_bufs,  1, 0 }, \
-      	[DRM_IOCTL_NR(DRM_IOCTL_I830_FLUSH)]  = { i830_flush_ioctl, 1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETAGE)] = { i830_getage,      1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_I830_GETBUF)] = { i830_getbuf,      1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_SWAP)]   = { i830_swap_bufs,   1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_COPY)]   = { i830_copybuf,     1, 0 }, \
-   	[DRM_IOCTL_NR(DRM_IOCTL_I830_DOCOPY)] = { i830_docopy,      1, 0 },
-
-#define __HAVE_COUNTERS         4
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#define __HAVE_COUNTER9         _DRM_STAT_DMA
-
-
-#include "drm_agpsupport.h"
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-#ifndef MODULE
-/* DRM(options) is called by the kernel to parse command-line options
- * passed via the boot-loader (e.g., LILO).  It calls the insmod option
- * routine, drm_parse_drm.
- */
-
-/* JH- We have to hand expand the string ourselves because of the cpp.  If
- * anyone can think of a way that we can fit into the __setup macro without
- * changing it, then please send the solution my way.
- */
-static int __init i830_options( char *str )
-{
-   DRM(parse_options)( str );
-   return 1;
-}
-
-__setup( DRIVER_NAME "=", i830_options );
-#endif
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lock.h"
-#include "drm_lists.h"
-#include "drm_memory.h"
-#include "drm_proc.h"
-#include "drm_vm.h"
-#include "drm_stub.h"
diff --git a/bsd/mga/mga_dma.c b/bsd/mga/mga_dma.c
deleted file mode 100644
index d9449c53..00000000
--- a/bsd/mga/mga_dma.c
+++ /dev/null
@@ -1,821 +0,0 @@
-/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
- * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Keith Whitwell <keithw@valinux.com>
- *
- * Rewritten by:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-
-
-#define MGA_DEFAULT_USEC_TIMEOUT	10000
-#define MGA_FREELIST_DEBUG		0
-
-
-/* ================================================================
- * Engine control
- */
-
-int mga_do_wait_for_idle( drm_mga_private_t *dev_priv )
-{
-	u32 status = 0;
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) {
-			MGA_WRITE8( MGA_CRTC_INDEX, 0 );
-			return 0;
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if MGA_DMA_DEBUG
-	DRM_ERROR( "failed!\n" );
-	DRM_INFO( "   status=0x%08x\n", status );
-#endif
-	DRM_OS_RETURN(EBUSY);
-}
-
-int mga_do_dma_idle( drm_mga_private_t *dev_priv )
-{
-	u32 status = 0;
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		status = MGA_READ( MGA_STATUS ) & MGA_DMA_IDLE_MASK;
-		if ( status == MGA_ENDPRDMASTS ) return 0;
-		DRM_OS_DELAY( 1 );
-	}
-
-#if MGA_DMA_DEBUG
-	DRM_ERROR( "failed! status=0x%08x\n", status );
-#endif
-	DRM_OS_RETURN(EBUSY);
-}
-
-int mga_do_dma_reset( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The primary DMA stream should look like new right about now.
-	 */
-	primary->tail = 0;
-	primary->space = primary->size;
-	primary->last_flush = 0;
-
-	sarea_priv->last_wrap = 0;
-
-	/* FIXME: Reset counters, buffer ages etc...
-	 */
-
-	/* FIXME: What else do we need to reinitialize?  WARP stuff?
-	 */
-
-	return 0;
-}
-
-int mga_do_engine_reset( drm_mga_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* Okay, so we've completely screwed up and locked the engine.
-	 * How about we clean up after ourselves?
-	 */
-	MGA_WRITE( MGA_RST, MGA_SOFTRESET );
-	DRM_OS_DELAY( 15 );		/* Wait at least 10 usecs */
-	MGA_WRITE( MGA_RST, 0 );
-
-	/* Initialize the registers that get clobbered by the soft
-	 * reset.  Many of the core register values survive a reset,
-	 * but the drawing registers are basically all gone.
-	 *
-	 * 3D clients should probably die after calling this.  The X
-	 * server should reset the engine state to known values.
-	 */
-#if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status_page) |
-		   MGA_PRIMPTREN0 |
-		   MGA_PRIMPTREN1 );
-#endif
-
-	MGA_WRITE( MGA_ICLEAR, MGA_SOFTRAPICLR );
-	MGA_WRITE( MGA_IEN,    MGA_SOFTRAPIEN );
-
-	/* The primary DMA stream should look like new right about now.
-	 */
-	mga_do_dma_reset( dev_priv );
-
-	/* This bad boy will never fail.
-	 */
-	return 0;
-}
-
-
-/* ================================================================
- * Primary DMA stream
- */
-
-void mga_do_dma_flush( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	u32 head, tail;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	if ( primary->tail == primary->last_flush ) {
-		DRM_DEBUG( "   bailing out...\n" );
-		return;
-	}
-
-	tail = primary->tail + dev_priv->primary->offset;
-
-	/* We need to pad the stream between flushes, as the card
-	 * actually (partially?) reads the first of these commands.
-	 * See page 4-16 in the G400 manual, middle of the page or so.
-	 */
-	BEGIN_DMA( 1 );
-
-	DMA_BLOCK( MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,  0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	ADVANCE_DMA();
-
-	primary->last_flush = primary->tail;
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-
-	if ( head <= tail ) {
-		primary->space = primary->size - primary->tail;
-	} else {
-		primary->space = head - tail;
-	}
-
-	DRM_DEBUG( "   head = 0x%06lx\n", head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06lx\n", tail - dev_priv->primary->offset );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
-
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	u32 head, tail;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	BEGIN_DMA_WRAP();
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	ADVANCE_DMA();
-
-	tail = primary->tail + dev_priv->primary->offset;
-
-	primary->tail = 0;
-	primary->last_flush = 0;
-	primary->last_wrap++;
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-
-	if ( head == dev_priv->primary->offset ) {
-		primary->space = primary->size;
-	} else {
-		primary->space = head - dev_priv->primary->offset;
-	}
-
-	DRM_DEBUG( "   head = 0x%06lx\n",
-		  head - dev_priv->primary->offset );
-	DRM_DEBUG( "   tail = 0x%06x\n", primary->tail );
-	DRM_DEBUG( "   wrap = %d\n", primary->last_wrap );
-	DRM_DEBUG( "  space = 0x%06x\n", primary->space );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMEND, tail | MGA_PAGPXFER );
-
-	set_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv )
-{
-	drm_mga_primary_buffer_t *primary = &dev_priv->prim;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 head = dev_priv->primary->offset;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	sarea_priv->last_wrap++;
-	DRM_DEBUG( "   wrap = %d\n", sarea_priv->last_wrap );
-
-	mga_flush_write_combine();
-	MGA_WRITE( MGA_PRIMADDRESS, head | MGA_DMA_GENERAL );
-
-	clear_bit( 0, &primary->wrapped );
-	DRM_DEBUG( "%s: done.\n", __FUNCTION__ );
-}
-
-
-/* ================================================================
- * Freelist management
- */
-
-#define MGA_BUFFER_USED		~0
-#define MGA_BUFFER_FREE		0
-
-#if MGA_FREELIST_DEBUG
-static void mga_freelist_print( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *entry;
-
-	DRM_INFO( "\n" );
-	DRM_INFO( "current dispatch: last=0x%x done=0x%x\n",
-		  dev_priv->sarea_priv->last_dispatch,
-		  (unsigned int)(MGA_READ( MGA_PRIMADDRESS ) -
-				 dev_priv->primary->offset) );
-	DRM_INFO( "current freelist:\n" );
-
-	for ( entry = dev_priv->head->next ; entry ; entry = entry->next ) {
-		DRM_INFO( "   %p   idx=%2d  age=0x%x 0x%06lx\n",
-			  entry, entry->buf->idx, entry->age.head,
-			  entry->age.head - dev_priv->primary->offset );
-	}
-	DRM_INFO( "\n" );
-}
-#endif
-
-static int mga_freelist_init( drm_device_t *dev, drm_mga_private_t *dev_priv )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_freelist_t *entry;
-	int i;
-	DRM_DEBUG( "%s: count=%d\n",
-		   __FUNCTION__, dma->buf_count );
-
-	dev_priv->head = DRM(alloc)( sizeof(drm_mga_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
-		DRM_OS_RETURN(ENOMEM);
-
-	memset( dev_priv->head, 0, sizeof(drm_mga_freelist_t) );
-	SET_AGE( &dev_priv->head->age, MGA_BUFFER_USED, 0 );
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
-
-		entry = DRM(alloc)( sizeof(drm_mga_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( entry == NULL )
-			DRM_OS_RETURN(ENOMEM);
-
-		memset( entry, 0, sizeof(drm_mga_freelist_t) );
-
-		entry->next = dev_priv->head->next;
-		entry->prev = dev_priv->head;
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
-		entry->buf = buf;
-
-		if ( dev_priv->head->next != NULL )
-			dev_priv->head->next->prev = entry;
-		if ( entry->next == NULL )
-			dev_priv->tail = entry;
-
-		buf_priv->list_entry = entry;
-		buf_priv->discard = 0;
-		buf_priv->dispatched = 0;
-
-		dev_priv->head->next = entry;
-	}
-
-	return 0;
-}
-
-static void mga_freelist_cleanup( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *entry;
-	drm_mga_freelist_t *next;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	entry = dev_priv->head;
-	while ( entry ) {
-		next = entry->next;
-		DRM(free)( entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER );
-		entry = next;
-	}
-
-	dev_priv->head = dev_priv->tail = NULL;
-}
-
-#if 0
-/* FIXME: Still needed?
- */
-static void mga_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	int i;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-	        buf_priv = buf->dev_private;
-		SET_AGE( &buf_priv->list_entry->age,
-			 MGA_BUFFER_FREE, 0 );
-	}
-}
-#endif
-
-static drm_buf_t *mga_freelist_get( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_freelist_t *next;
-	drm_mga_freelist_t *prev;
-	drm_mga_freelist_t *tail = dev_priv->tail;
-	u32 head, wrap;
-	DRM_DEBUG( "%s:\n", __FUNCTION__ );
-
-	head = MGA_READ( MGA_PRIMADDRESS );
-	wrap = dev_priv->sarea_priv->last_wrap;
-
-	DRM_DEBUG( "   tail=0x%06lx %d\n",
-		   tail->age.head ?
-		   tail->age.head - dev_priv->primary->offset : 0,
-		   tail->age.wrap );
-	DRM_DEBUG( "   head=0x%06lx %d\n",
-		   head - dev_priv->primary->offset, wrap );
-
-	if ( TEST_AGE( &tail->age, head, wrap ) ) {
-		prev = dev_priv->tail->prev;
-		next = dev_priv->tail;
-		prev->next = NULL;
-		next->prev = next->next = NULL;
-		dev_priv->tail = prev;
-		SET_AGE( &next->age, MGA_BUFFER_USED, 0 );
-		return next->buf;
-	}
-
-	DRM_DEBUG( "returning NULL!\n" );
-	return NULL;
-}
-
-int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_freelist_t *head, *entry, *prev;
-
-	DRM_DEBUG( "%s: age=0x%06lx wrap=%d\n",
-		   __FUNCTION__,
-		   buf_priv->list_entry->age.head -
-		   dev_priv->primary->offset,
-		   buf_priv->list_entry->age.wrap );
-
-	entry = buf_priv->list_entry;
-	head = dev_priv->head;
-
-	if ( buf_priv->list_entry->age.head == MGA_BUFFER_USED ) {
-		SET_AGE( &entry->age, MGA_BUFFER_FREE, 0 );
-		prev = dev_priv->tail;
-		prev->next = entry;
-		entry->prev = prev;
-		entry->next = NULL;
-	} else {
-		prev = head->next;
-		head->next = entry;
-		prev->prev = entry;
-		entry->prev = head;
-		entry->next = prev;
-	}
-
-	return 0;
-}
-
-
-/* ================================================================
- * DMA initialization, cleanup
- */
-
-static int mga_do_init_dma( drm_device_t *dev, drm_mga_init_t *init )
-{
-	drm_mga_private_t *dev_priv;
-	drm_map_list_entry_t *listentry;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_mga_private_t), DRM_MEM_DRIVER );
-	if ( !dev_priv )
-		DRM_OS_RETURN(ENOMEM);
-
-	memset( dev_priv, 0, sizeof(drm_mga_private_t) );
-
-	dev_priv->chipset = init->chipset;
-
-	dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
-
-	if ( init->sgram ) {
-		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
-	} else {
-		dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
-	}
-	dev_priv->maccess	= init->maccess;
-
-	dev_priv->fb_cpp	= init->fb_cpp;
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	dev_priv->depth_cpp	= init->depth_cpp;
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-
-	/* FIXME: Need to support AGP textures...
-	 */
-	dev_priv->texture_offset = init->texture_offset[0];
-	dev_priv->texture_size = init->texture_size[0];
-
-	TAILQ_FOREACH(listentry, dev->maplist, link) {
-		drm_map_t *map = listentry->map;
-		if (map->type == _DRM_SHM &&
-			map->flags & _DRM_CONTAINS_LOCK) {
-			dev_priv->sarea = map;
-			break;
-		}
-	}
-
-	if(!dev_priv->sarea) {
-		DRM_ERROR( "failed to find sarea!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR( "failed to find framebuffer!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR( "failed to find mmio region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->status, init->status_offset );
-	if(!dev_priv->status) {
-		DRM_ERROR( "failed to find status page!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->warp, init->warp_offset );
-	if(!dev_priv->warp) {
-		DRM_ERROR( "failed to find warp microcode region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->primary, init->primary_offset );
-	if(!dev_priv->primary) {
-		DRM_ERROR( "failed to find primary dma region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR( "failed to find dma buffer region!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	dev_priv->sarea_priv =
-		(drm_mga_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				    init->sarea_priv_offset);
-
-	DRM_IOREMAP( dev_priv->warp );
-	DRM_IOREMAP( dev_priv->primary );
-	DRM_IOREMAP( dev_priv->buffers );
-
-	if(!dev_priv->warp->handle ||
-	   !dev_priv->primary->handle ||
-	   !dev_priv->buffers->handle ) {
-		DRM_ERROR( "failed to ioremap agp regions!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(ENOMEM);
-	}
-
-	ret = mga_warp_install_microcode( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to install WARP ucode!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(ret);
-	}
-
-	ret = mga_warp_init( dev_priv );
-	if ( ret < 0 ) {
-		DRM_ERROR( "failed to init WARP engine!\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(ret);
-	}
-
-	dev_priv->prim.status = (u32 *)dev_priv->status->handle;
-
-	mga_do_wait_for_idle( dev_priv );
-
-	/* Init the primary DMA registers.
-	 */
-	MGA_WRITE( MGA_PRIMADDRESS,
-		   dev_priv->primary->offset | MGA_DMA_GENERAL );
-#if 0
-	MGA_WRITE( MGA_PRIMPTR,
-		   virt_to_bus((void *)dev_priv->prim.status) |
-		   MGA_PRIMPTREN0 |	/* Soft trap, SECEND, SETUPEND */
-		   MGA_PRIMPTREN1 );	/* DWGSYNC */
-#endif
-
-	dev_priv->prim.start = (u8 *)dev_priv->primary->handle;
-	dev_priv->prim.end = ((u8 *)dev_priv->primary->handle
-			      + dev_priv->primary->size);
-	dev_priv->prim.size = dev_priv->primary->size;
-
-	dev_priv->prim.tail = 0;
-	dev_priv->prim.space = dev_priv->prim.size;
-	dev_priv->prim.wrapped = 0;
-
-	dev_priv->prim.last_flush = 0;
-	dev_priv->prim.last_wrap = 0;
-
-	dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
-
-
-	dev_priv->prim.status[0] = dev_priv->primary->offset;
-	dev_priv->prim.status[1] = 0;
-
-	dev_priv->sarea_priv->last_wrap = 0;
-	dev_priv->sarea_priv->last_frame.head = 0;
-	dev_priv->sarea_priv->last_frame.wrap = 0;
-
-	if ( mga_freelist_init( dev, dev_priv ) < 0 ) {
-		DRM_ERROR( "could not initialize freelist\n" );
-		/* Assign dev_private so we can do cleanup. */
-		dev->dev_private = (void *)dev_priv;
-		mga_do_cleanup_dma( dev );
-		DRM_OS_RETURN(ENOMEM);
-	}
-
-	/* Make dev_private visable to others. */
-	dev->dev_private = (void *)dev_priv;
-	return 0;
-}
-
-int mga_do_cleanup_dma( drm_device_t *dev )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev->dev_private ) {
-		drm_mga_private_t *dev_priv = dev->dev_private;
-
-		DRM_IOREMAPFREE( dev_priv->warp );
-		DRM_IOREMAPFREE( dev_priv->primary );
-		DRM_IOREMAPFREE( dev_priv->buffers );
-
-		if ( dev_priv->head != NULL ) {
-			mga_freelist_cleanup( dev );
-		}
-
-		DRM(free)( dev->dev_private, sizeof(drm_mga_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int mga_dma_init( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_init_t init;
-
-	DRM_OS_KRNFROMUSR( init, (drm_mga_init_t *) data, sizeof(init) );
-
-	switch ( init.func ) {
-	case MGA_INIT_DMA:
-		return mga_do_init_dma( dev, &init );
-	case MGA_CLEANUP_DMA:
-		return mga_do_cleanup_dma( dev );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-
-/* ================================================================
- * Primary DMA stream management
- */
-
-int mga_dma_flush( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-	drm_lock_t lock;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( lock, (drm_lock_t *) data, sizeof(lock) );
-
-	DRM_DEBUG( "%s: %s%s%s\n",
-		   __FUNCTION__,
-		   (lock.flags & _DRM_LOCK_FLUSH) ?	"flush, " : "",
-		   (lock.flags & _DRM_LOCK_FLUSH_ALL) ?	"flush all, " : "",
-		   (lock.flags & _DRM_LOCK_QUIESCENT) ?	"idle, " : "" );
-
-	WRAP_WAIT_WITH_RETURN( dev_priv );
-
-	if ( lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL) ) {
-		mga_do_dma_flush( dev_priv );
-	}
-
-	if ( lock.flags & _DRM_LOCK_QUIESCENT ) {
-#if MGA_DMA_DEBUG
-		int ret = mga_do_wait_for_idle( dev_priv );
-		if ( ret )
-			DRM_INFO( __FUNCTION__": -EBUSY\n" );
-		return ret;
-#else
-		return mga_do_wait_for_idle( dev_priv );
-#endif
-	} else {
-		return 0;
-	}
-}
-
-int mga_dma_reset( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return mga_do_dma_reset( dev_priv );
-}
-
-
-/* ================================================================
- * DMA buffer management
- */
-
-#if 0
-static int mga_dma_get_buffers( drm_device_t *dev, drm_dma_t *d )
-{
-	drm_buf_t *buf;
-	int i;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = mga_freelist_get( dev );
-		if ( !buf )
-			DRM_OS_RETURN( EAGAIN );
-
-		buf->pid = current->pid;
-
-		if ( DRM_OS_COPYTOUSR( &d->request_indices[i],
-				   &buf->idx, sizeof(buf->idx) ) )
-			DRM_OS_RETURN( EFAULT );
-		if ( DRM_OS_COPYTOUSR( &d->request_sizes[i],
-				   &buf->total, sizeof(buf->total) ) )
-			DRM_OS_RETURN( EFAULT );
-
-		d->granted_count++;
-	}
-	return 0;
-}
-#endif /* 0 */
-
-int mga_dma_buffers( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-	drm_mga_private_t *dev_priv = (drm_mga_private_t *)dev->dev_private;
-	drm_dma_t d;
-	drm_buf_t *buf;
-	int i;
-	int ret = 0;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) );
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_OS_CURRENTPID, d.send_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_OS_CURRENTPID, d.request_count, dma->buf_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		for ( i = d.granted_count ; i < d.request_count ; i++ ) {
-			buf = mga_freelist_get( dev );
-			if ( !buf )
-				DRM_OS_RETURN( EAGAIN );
-
-			buf->pid = DRM_OS_CURRENTPID;
-
-			if ( DRM_OS_COPYTOUSR( &d.request_indices[i],
-					   &buf->idx, sizeof(buf->idx) ) )
-				DRM_OS_RETURN( EFAULT );
-			if ( DRM_OS_COPYTOUSR( &d.request_sizes[i],
-					   &buf->total, sizeof(buf->total) ) )
-				DRM_OS_RETURN( EFAULT );
-	
-			d.granted_count++;
-		}
-		ret = 0;
-	}
-
-	DRM_OS_KRNTOUSR( (drm_dma_t *) data, d, sizeof(d) );
-
-	return ret;
-}
diff --git a/bsd/mga/mga_drv.c b/bsd/mga/mga_drv.c
deleted file mode 100644
index d8af2236..00000000
--- a/bsd/mga/mga_drv.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/* mga_drv.c -- Matrox G200/G400 driver -*- linux-c -*-
- * Created: Mon Dec 13 01:56:22 1999 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-
-#include <sys/types.h>
-#include <sys/bus.h>
-#include <pci/pcivar.h>
-#include <opt_drm_linux.h>
-
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"mga"
-#define DRIVER_DESC		"Matrox G200/G400"
-#define DRIVER_DATE		"20010321"
-
-#define DRIVER_MAJOR		3
-#define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	2
-
-/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
- * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here.
- */
-drm_chipinfo_t DRM(devicelist)[] = {
-	{0x102b, 0x0520, 0, "Matrox G200 (PCI)"},
-	{0x102b, 0x0521, 1, "Matrox G200 (AGP)"},
-	{0x102b, 0x0525, 1, "Matrox G400 (AGP)"},
-	{0, 0, 0, NULL}
-};
-
-#define DRIVER_IOCTLS							   \
-	[DRM_IOCTL_NR(DRM_IOCTL_DMA)]	      = { mga_dma_buffers, 1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INIT)]    = { mga_dma_init,    1, 1 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_FLUSH)]   = { mga_dma_flush,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_RESET)]   = { mga_dma_reset,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_SWAP)]    = { mga_dma_swap,    1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_CLEAR)]   = { mga_dma_clear,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_VERTEX)]  = { mga_dma_vertex,  1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_INDICES)] = { mga_dma_indices, 1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_ILOAD)]   = { mga_dma_iload,   1, 0 }, \
-	[DRM_IOCTL_NR(DRM_IOCTL_MGA_BLIT)]    = { mga_dma_blit,    1, 0 },
-
-
-#define __HAVE_COUNTERS         3
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-
-
-#include "drm_agpsupport.h"
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lock.h"
-#include "drm_memory.h"
-#include "drm_vm.h"
-#include "drm_sysctl.h"
-
-DRIVER_MODULE(mga, pci, mga_driver, mga_devclass, 0, 0);
diff --git a/bsd/mga/mga_state.c b/bsd/mga/mga_state.c
deleted file mode 100644
index a0bd404a..00000000
--- a/bsd/mga/mga_state.c
+++ /dev/null
@@ -1,1076 +0,0 @@
-/* mga_state.c -- State support for MGA G200/G400 -*- linux-c -*-
- * Created: Thu Jan 27 02:53:43 2000 by jhartmann@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Jeff Hartmann <jhartmann@valinux.com>
- *    Keith Whitwell <keithw@valinux.com>
- *
- * Rewritten by:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "drm.h"
-
-
-/* ================================================================
- * DMA hardware state programming functions
- */
-
-static void mga_emit_clip_rect( drm_mga_private_t *dev_priv,
-				drm_clip_rect_t *box )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	unsigned int pitch = dev_priv->front_pitch;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 2 );
-
-	/* Force reset of DWGCTL on G400 (eliminates clip disable bit).
-	 */
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		DMA_BLOCK( MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000,
-			   MGA_DWGCTL,		ctx->dwgctl,
-			   MGA_LEN + MGA_EXEC,	0x80000000 );
-	}
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_CXBNDRY,	(box->x2 << 16) | box->x1,
-		   MGA_YTOP,	box->y1 * pitch,
-		   MGA_YBOT,	box->y2 * pitch );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g200_emit_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 3 );
-
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
-
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
-
-	DMA_BLOCK( MGA_FCOL,		ctx->fcol,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g400_emit_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 4 );
-
-	DMA_BLOCK( MGA_DSTORG,		ctx->dstorg,
-		   MGA_MACCESS,		ctx->maccess,
-		   MGA_PLNWT,		ctx->plnwt,
-		   MGA_DWGCTL,		ctx->dwgctl );
-
-	DMA_BLOCK( MGA_ALPHACTRL,	ctx->alphactrl,
-		   MGA_FOGCOL,		ctx->fogcolor,
-		   MGA_WFLAG,		ctx->wflag,
-		   MGA_ZORG,		dev_priv->depth_offset );
-
-	DMA_BLOCK( MGA_WFLAG1,		ctx->wflag,
-		   MGA_TDUALSTAGE0,	ctx->tdualstage0,
-		   MGA_TDUALSTAGE1,	ctx->tdualstage1,
-		   MGA_FCOL,		ctx->fcol );
-
-	DMA_BLOCK( MGA_STENCIL,		ctx->stencil,
-		   MGA_STENCILCTL,	ctx->stencilctl,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g200_emit_tex0( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	DMA_LOCALS;
-
-	BEGIN_DMA( 4 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR24,		tex->texwidth );
-
-	DMA_BLOCK( MGA_WR34,		tex->texheight,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_DMAPAD,		0x00000000 );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g400_emit_tex0( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_tex0 %x %x %x\n", tex->texorg, */
-/*  	       tex->texctl, tex->texctl2); */
-
-	BEGIN_DMA( 6 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC,
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
-
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		MGA_G400_WR_MAGIC );
-
-	DMA_BLOCK( MGA_WR60,		MGA_G400_WR_MAGIC,
-		   MGA_WR54,		tex->texwidth | MGA_G400_WR_MAGIC,
-		   MGA_WR62,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_DMAPAD,		0x00000000 );
-
-	DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-		   MGA_DMAPAD,		0x00000000,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g400_emit_tex1( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_tex1 %x %x %x\n", tex->texorg,  */
-/*  	       tex->texctl, tex->texctl2); */
-
-	BEGIN_DMA( 5 );
-
-	DMA_BLOCK( MGA_TEXCTL2,		(tex->texctl2 |
-					 MGA_MAP1_ENABLE |
-					 MGA_G400_TC2_MAGIC),
-		   MGA_TEXCTL,		tex->texctl,
-		   MGA_TEXFILTER,	tex->texfilter,
-		   MGA_TEXBORDERCOL,	tex->texbordercol );
-
-	DMA_BLOCK( MGA_TEXORG,		tex->texorg,
-		   MGA_TEXORG1,		tex->texorg1,
-		   MGA_TEXORG2,		tex->texorg2,
-		   MGA_TEXORG3,		tex->texorg3 );
-
-	DMA_BLOCK( MGA_TEXORG4,		tex->texorg4,
-		   MGA_TEXWIDTH,	tex->texwidth,
-		   MGA_TEXHEIGHT,	tex->texheight,
-		   MGA_WR49,		0x00000000 );
-
-	DMA_BLOCK( MGA_WR57,		0x00000000,
-		   MGA_WR53,		0x00000000,
-		   MGA_WR61,		0x00000000,
-		   MGA_WR52,		tex->texwidth | MGA_G400_WR_MAGIC );
-
-	DMA_BLOCK( MGA_WR60,		tex->texheight | MGA_G400_WR_MAGIC,
-		   MGA_TEXTRANS,	0x0000ffff,
-		   MGA_TEXTRANSHIGH,	0x0000ffff,
-		   MGA_TEXCTL2,		tex->texctl2 | MGA_G400_TC2_MAGIC );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g200_emit_pipe( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int pipe = sarea_priv->warp_pipe;
-	DMA_LOCALS;
-
-	BEGIN_DMA( 3 );
-
-	DMA_BLOCK( MGA_WIADDR,	MGA_WMODE_SUSPEND,
-		   MGA_WVRTXSZ,	0x00000007,
-		   MGA_WFLAG,	0x00000000,
-		   MGA_WR24,	0x00000000 );
-
-	DMA_BLOCK( MGA_WR25,	0x00000100,
-		   MGA_WR34,	0x00000000,
-		   MGA_WR42,	0x0000ffff,
-		   MGA_WR60,	0x0000ffff );
-
-	/* Padding required to to hardware bug.
-	 */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
-
-	ADVANCE_DMA();
-}
-
-static __inline__ void mga_g400_emit_pipe( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int pipe = sarea_priv->warp_pipe;
-	DMA_LOCALS;
-
-/*  	printk("mga_g400_emit_pipe %x\n", pipe); */
-
-	BEGIN_DMA( 10 );
-
-	DMA_BLOCK( MGA_WIADDR2,	MGA_WMODE_SUSPEND,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000 );
-
-	if ( pipe & MGA_T2 ) {
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001e09,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
-
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x1e000000 );
-	} else {
-		if ( dev_priv->warp_pipe & MGA_T2 ) {
-			/* Flush the WARP pipe */
-			DMA_BLOCK( MGA_YDST,		0x00000000,
-				   MGA_FXLEFT,		0x00000000,
-				   MGA_FXRIGHT,		0x00000001,
-				   MGA_DWGCTL,		MGA_DWGCTL_FLUSH );
-
-			DMA_BLOCK( MGA_LEN + MGA_EXEC,	0x00000001,
-				   MGA_DWGSYNC,		0x00007000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_LEN + MGA_EXEC,	0x00000000 );
-
-			DMA_BLOCK( MGA_TEXCTL2,		(MGA_DUALTEX |
-							 MGA_G400_TC2_MAGIC),
-				   MGA_LEN + MGA_EXEC,	0x00000000,
-				   MGA_TEXCTL2,		MGA_G400_TC2_MAGIC,
-				   MGA_DMAPAD,		0x00000000 );
-		}
-
-		DMA_BLOCK( MGA_WVRTXSZ,		0x00001807,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000,
-			   MGA_DMAPAD,		0x00000000 );
-
-		DMA_BLOCK( MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x00000000,
-			   MGA_WACCEPTSEQ,	0x18000000 );
-	}
-
-	DMA_BLOCK( MGA_WFLAG,	0x00000000,
-		   MGA_WFLAG1,	0x00000000,
-		   MGA_WR56,	MGA_G400_WR56_MAGIC,
-		   MGA_DMAPAD,	0x00000000 );
-
-	DMA_BLOCK( MGA_WR49,	0x00000000,		/* tex0              */
-		   MGA_WR57,	0x00000000,		/* tex0              */
-		   MGA_WR53,	0x00000000,		/* tex1              */
-		   MGA_WR61,	0x00000000 );		/* tex1              */
-
-	DMA_BLOCK( MGA_WR54,	MGA_G400_WR_MAGIC,	/* tex0 width        */
-		   MGA_WR62,	MGA_G400_WR_MAGIC,	/* tex0 height       */
-		   MGA_WR52,	MGA_G400_WR_MAGIC,	/* tex1 width        */
-		   MGA_WR60,	MGA_G400_WR_MAGIC );	/* tex1 height       */
-
-	/* Padding required to to hardware bug */
-	DMA_BLOCK( MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_DMAPAD,	0xffffffff,
-		   MGA_WIADDR2,	(dev_priv->warp_pipe_phys[pipe] |
-				 MGA_WMODE_START |
-				 MGA_WAGP_ENABLE) );
-
-	ADVANCE_DMA();
-}
-
-static void mga_g200_emit_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g200_emit_pipe( dev_priv );
-		dev_priv->warp_pipe = sarea_priv->warp_pipe;
-	}
-
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g200_emit_context( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g200_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
-	}
-}
-
-static void mga_g400_emit_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-	int multitex = sarea_priv->warp_pipe & MGA_T2;
-
-	if ( sarea_priv->warp_pipe != dev_priv->warp_pipe ) {
-		mga_g400_emit_pipe( dev_priv );
-		dev_priv->warp_pipe = sarea_priv->warp_pipe;
-	}
-
-	if ( dirty & MGA_UPLOAD_CONTEXT ) {
-		mga_g400_emit_context( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & MGA_UPLOAD_TEX0 ) {
-		mga_g400_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
-	}
-
-	if ( (dirty & MGA_UPLOAD_TEX1) && multitex ) {
-		mga_g400_emit_tex1( dev_priv );
-		sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
-	}
-}
-
-
-/* ================================================================
- * SAREA state verification
- */
-
-/* Disallow all write destinations except the front and backbuffer.
- */
-static int mga_verify_context( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-
-	if ( ctx->dstorg != dev_priv->front_offset &&
-	     ctx->dstorg != dev_priv->back_offset ) {
-		DRM_ERROR( "*** bad DSTORG: %x (front %x, back %x)\n\n",
-			   ctx->dstorg, dev_priv->front_offset,
-			   dev_priv->back_offset );
-		ctx->dstorg = 0;
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	return 0;
-}
-
-/* Disallow texture reads from PCI space.
- */
-static int mga_verify_tex( drm_mga_private_t *dev_priv, int unit )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
-	unsigned int org;
-
-	org = tex->texorg & (MGA_TEXORGMAP_MASK | MGA_TEXORGACC_MASK);
-
-	if ( org == (MGA_TEXORGMAP_SYSMEM | MGA_TEXORGACC_PCI) ) {
-		DRM_ERROR( "*** bad TEXORG: 0x%x, unit %d\n",
-			   tex->texorg, unit );
-		tex->texorg = 0;
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	return 0;
-}
-
-static int mga_verify_state( drm_mga_private_t *dev_priv )
-{
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-	int ret = 0;
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	if ( dirty & MGA_UPLOAD_CONTEXT )
-		ret |= mga_verify_context( dev_priv );
-
-	if ( dirty & MGA_UPLOAD_TEX0 )
-		ret |= mga_verify_tex( dev_priv, 0 );
-
-	if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) {
-		if ( dirty & MGA_UPLOAD_TEX1 )
-			ret |= mga_verify_tex( dev_priv, 1 );
-
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G400_PIPES );
-	} else {
-		if ( dirty & MGA_UPLOAD_PIPE )
-			ret |= ( sarea_priv->warp_pipe > MGA_MAX_G200_PIPES );
-	}
-
-	return ( ret == 0 );
-}
-
-static int mga_verify_iload( drm_mga_private_t *dev_priv,
-			     unsigned int dstorg, unsigned int length )
-{
-	if ( dstorg < dev_priv->texture_offset ||
-	     dstorg + length > (dev_priv->texture_offset +
-				dev_priv->texture_size) ) {
-		DRM_ERROR( "*** bad iload DSTORG: 0x%x\n", dstorg );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if ( length & MGA_ILOAD_MASK ) {
-		DRM_ERROR( "*** bad iload length: 0x%x\n",
-			   length & MGA_ILOAD_MASK );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	return 0;
-}
-
-static int mga_verify_blit( drm_mga_private_t *dev_priv,
-			    unsigned int srcorg, unsigned int dstorg )
-{
-	if ( (srcorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ||
-	     (dstorg & 0x3) == (MGA_SRCACC_PCI | MGA_SRCMAP_SYSMEM) ) {
-		DRM_ERROR( "*** bad blit: src=0x%x dst=0x%x\n",
-			   srcorg, dstorg );
-		DRM_OS_RETURN( EINVAL );
-	}
-	return 0;
-}
-
-
-/* ================================================================
- *
- */
-
-static void mga_dma_dispatch_clear( drm_device_t *dev,
-				    drm_mga_clear_t *clear )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	int i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	BEGIN_DMA( 1 );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	ADVANCE_DMA();
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		drm_clip_rect_t *box = &pbox[i];
-		u32 height = box->y2 - box->y1;
-
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
-
-		if ( clear->flags & MGA_FRONT ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->front_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-
-		if ( clear->flags & MGA_BACK ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->color_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_color,
-				   MGA_DSTORG,	dev_priv->back_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-		if ( clear->flags & MGA_DEPTH ) {
-			BEGIN_DMA( 2 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_PLNWT,	clear->depth_mask,
-				   MGA_YDSTLEN, (box->y1 << 16) | height,
-				   MGA_FXBNDRY, (box->x2 << 16) | box->x1 );
-
-			DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-				   MGA_FCOL,	clear->clear_depth,
-				   MGA_DSTORG,	dev_priv->depth_offset,
-				   MGA_DWGCTL + MGA_EXEC,
-						dev_priv->clear_cmd );
-
-			ADVANCE_DMA();
-		}
-
-	}
-
-	BEGIN_DMA( 1 );
-
-	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_swap( drm_device_t *dev )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	int i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	sarea_priv->last_frame.head = dev_priv->prim.tail;
-	sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
-
-	BEGIN_DMA( 4 + nbox );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DSTORG,	dev_priv->front_offset,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_SRCORG,	dev_priv->back_offset,
-		   MGA_AR5,	dev_priv->front_pitch );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		drm_clip_rect_t *box = &pbox[i];
-		u32 height = box->y2 - box->y1;
-		u32 start = box->y1 * dev_priv->front_pitch;
-
-		DRM_DEBUG( "   from=%d,%d to=%d,%d\n",
-			   box->x1, box->y1, box->x2, box->y2 );
-
-		DMA_BLOCK( MGA_AR0,	start + box->x2 - 1,
-			   MGA_AR3,	start + box->x1,
-			   MGA_FXBNDRY,	((box->x2 - 1) << 16) | box->x1,
-			   MGA_YDSTLEN + MGA_EXEC,
-					(box->y1 << 16) | height );
-	}
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-
-	FLUSH_DMA();
-
-	DRM_DEBUG( "%s... done.\n", __FUNCTION__ );
-}
-
-static void mga_dma_dispatch_vertex( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 address = (u32) buf->bus_address;
-	u32 length = (u32) buf->used;
-	int i = 0;
-	DMA_LOCALS;
-	DRM_DEBUG( "vertex: buf=%d used=%d\n", buf->idx, buf->used );
-
-	if ( buf->used ) {
-		buf_priv->dispatched = 1;
-
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
-
-		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
-			}
-
-			BEGIN_DMA( 1 );
-
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SECADDRESS,	(address |
-							 MGA_DMA_VERTEX),
-				   MGA_SECEND,		((address + length) |
-							 MGA_PAGPXFER) );
-
-			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
-		buf->pending = 0;
-		buf->used = 0;
-		buf_priv->dispatched = 0;
-
-		mga_freelist_put( dev, buf );
-	}
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_indices( drm_device_t *dev, drm_buf_t *buf,
-				      unsigned int start, unsigned int end )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	u32 address = (u32) buf->bus_address;
-	int i = 0;
-	DMA_LOCALS;
-	DRM_DEBUG( "indices: buf=%d start=%d end=%d\n", buf->idx, start, end );
-
-	if ( start != end ) {
-		buf_priv->dispatched = 1;
-
-		MGA_EMIT_STATE( dev_priv, sarea_priv->dirty );
-
-		do {
-			if ( i < sarea_priv->nbox ) {
-				mga_emit_clip_rect( dev_priv,
-						    &sarea_priv->boxes[i] );
-			}
-
-			BEGIN_DMA( 1 );
-
-			DMA_BLOCK( MGA_DMAPAD,		0x00000000,
-				   MGA_DMAPAD,		0x00000000,
-				   MGA_SETUPADDRESS,	address + start,
-				   MGA_SETUPEND,	((address + end) |
-							 MGA_PAGPXFER) );
-
-			ADVANCE_DMA();
-		} while ( ++i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		AGE_BUFFER( buf_priv );
-		buf->pending = 0;
-		buf->used = 0;
-		buf_priv->dispatched = 0;
-
-		mga_freelist_put( dev, buf );
-	}
-
-	FLUSH_DMA();
-}
-
-/* This copies a 64 byte aligned agp region to the frambuffer with a
- * standard blit, the ioctl needs to do checking.
- */
-static void mga_dma_dispatch_iload( drm_device_t *dev, drm_buf_t *buf,
-				    unsigned int dstorg, unsigned int length )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_buf_priv_t *buf_priv = buf->dev_private;
-	drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
-	u32 srcorg = buf->bus_address | MGA_SRCACC_AGP | MGA_SRCMAP_SYSMEM;
-	u32 y2;
-	DMA_LOCALS;
-	DRM_DEBUG( "%s: buf=%d used=%d\n",
-		   __FUNCTION__, buf->idx, buf->used );
-
-	y2 = length / 64;
-
-	BEGIN_DMA( 5 );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DSTORG,	dstorg,
-		   MGA_MACCESS,	0x00000000,
-		   MGA_SRCORG,	srcorg,
-		   MGA_AR5,	64 );
-
-	DMA_BLOCK( MGA_PITCH,	64,
-		   MGA_PLNWT,	0xffffffff,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGCTL,	MGA_DWGCTL_COPY );
-
-	DMA_BLOCK( MGA_AR0,	63,
-		   MGA_AR3,	0,
-		   MGA_FXBNDRY,	(63 << 16) | 0,
-		   MGA_YDSTLEN + MGA_EXEC, y2 );
-
-	DMA_BLOCK( MGA_PLNWT,	ctx->plnwt,
-		   MGA_SRCORG,	dev_priv->front_offset,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	ADVANCE_DMA();
-
-	AGE_BUFFER( buf_priv );
-
-	buf->pending = 0;
-	buf->used = 0;
-	buf_priv->dispatched = 0;
-
-	mga_freelist_put( dev, buf );
-
-	FLUSH_DMA();
-}
-
-static void mga_dma_dispatch_blit( drm_device_t *dev,
-				   drm_mga_blit_t *blit )
-{
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int nbox = sarea_priv->nbox;
-	u32 scandir = 0, i;
-	DMA_LOCALS;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	BEGIN_DMA( 4 + nbox );
-
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_DMAPAD,	0x00000000,
-		   MGA_DWGSYNC,	0x00007100,
-		   MGA_DWGSYNC,	0x00007000 );
-
-	DMA_BLOCK( MGA_DWGCTL,	MGA_DWGCTL_COPY,
-		   MGA_PLNWT,	blit->planemask,
-		   MGA_SRCORG,	blit->srcorg,
-		   MGA_DSTORG,	blit->dstorg );
-
-	DMA_BLOCK( MGA_SGN,	scandir,
-		   MGA_MACCESS,	dev_priv->maccess,
-		   MGA_AR5,	blit->ydir * blit->src_pitch,
-		   MGA_PITCH,	blit->dst_pitch );
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int srcx = pbox[i].x1 + blit->delta_sx;
-		int srcy = pbox[i].y1 + blit->delta_sy;
-		int dstx = pbox[i].x1 + blit->delta_dx;
-		int dsty = pbox[i].y1 + blit->delta_dy;
-		int h = pbox[i].y2 - pbox[i].y1;
-		int w = pbox[i].x2 - pbox[i].x1 - 1;
-		int start;
-
-		if ( blit->ydir == -1 ) {
-			srcy = blit->height - srcy - 1;
-		}
-
-		start = srcy * blit->src_pitch + srcx;
-
-		DMA_BLOCK( MGA_AR0,	start + w,
-			   MGA_AR3,	start,
-			   MGA_FXBNDRY,	((dstx + w) << 16) | (dstx & 0xffff),
-			   MGA_YDSTLEN + MGA_EXEC, (dsty << 16) | h );
-	}
-
-	/* Do something to flush AGP?
-	 */
-
-	/* Force reset of DWGCTL */
-	DMA_BLOCK( MGA_DMAPAD,	0x00000000,
-		   MGA_PLNWT,	ctx->plnwt,
-		   MGA_PITCH,	dev_priv->front_pitch,
-		   MGA_DWGCTL,	ctx->dwgctl );
-
-	ADVANCE_DMA();
-}
-
-
-/* ================================================================
- *
- */
-
-int mga_dma_clear( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_clear_t clear;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( clear, (drm_mga_clear_t *) data, sizeof(clear) );
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_clear( dev, &clear );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_swap( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_swap( dev );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_vertex( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_vertex_t vertex;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( vertex, (drm_mga_vertex_t *) data, sizeof(vertex) );
-
-        if(vertex.idx < 0 || vertex.idx > dma->buf_count) DRM_OS_RETURN( EINVAL );
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	buf->used = vertex.used;
-	buf_priv->discard = vertex.discard;
-
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( vertex.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
-			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
-		}
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_vertex( dev, buf );
-
-	return 0;
-}
-
-int mga_dma_indices( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_indices_t indices;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( indices, (drm_mga_indices_t *) data, sizeof(indices) );
-
-        if(indices.idx < 0 || indices.idx > dma->buf_count) DRM_OS_RETURN( EINVAL );
-
-	buf = dma->buflist[indices.idx];
-	buf_priv = buf->dev_private;
-
-	buf_priv->discard = indices.discard;
-
-	if ( !mga_verify_state( dev_priv ) ) {
-		if ( indices.discard ) {
-			if ( buf_priv->dispatched == 1 )
-				AGE_BUFFER( buf_priv );
-			buf_priv->dispatched = 0;
-			mga_freelist_put( dev, buf );
-		}
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_indices( dev, buf, indices.start, indices.end );
-
-	return 0;
-}
-
-int mga_dma_iload( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_mga_buf_priv_t *buf_priv;
-	drm_mga_iload_t iload;
-	DRM_DEBUG( __FUNCTION__ ":\n" );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( iload, (drm_mga_iload_t *) data, sizeof(iload) );
-
-#if 0
-	if ( mga_do_wait_for_idle( dev_priv ) ) {
-		if ( MGA_DMA_DEBUG )
-			DRM_INFO( __FUNCTION__": -EBUSY\n" );
-		DRM_OS_RETURN( EBUSY );
-	}
-#endif
-        if(iload.idx < 0 || iload.idx > dma->buf_count) DRM_OS_RETURN( EINVAL );
-
-	buf = dma->buflist[iload.idx];
-	buf_priv = buf->dev_private;
-
-	if ( mga_verify_iload( dev_priv, iload.dstorg, iload.length ) ) {
-		mga_freelist_put( dev, buf );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_iload( dev, buf, iload.dstorg, iload.length );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
-
-int mga_dma_blit( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_mga_private_t *dev_priv = dev->dev_private;
-	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_mga_blit_t blit;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( blit, (drm_mga_blit_t *) data, sizeof(blit) );
-
-	if ( sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
-
-	if ( mga_verify_blit( dev_priv, blit.srcorg, blit.dstorg ) )
-		DRM_OS_RETURN( EINVAL );
-
-	WRAP_TEST_WITH_RETURN( dev_priv );
-
-	mga_dma_dispatch_blit( dev, &blit );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
-
-	return 0;
-}
diff --git a/bsd/mga/mga_warp.c b/bsd/mga/mga_warp.c
deleted file mode 100644
index f11cd922..00000000
--- a/bsd/mga/mga_warp.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
- * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "mga.h"
-#include "drmP.h"
-#include "drm.h"
-#include "mga_drm.h"
-#include "mga_drv.h"
-#include "mga_ucode.h"
-
-
-#define MGA_WARP_CODE_ALIGN		256		/* in bytes */
-
-#define WARP_UCODE_SIZE( which )					\
-	((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
-
-#define WARP_UCODE_INSTALL( which, where )				\
-do {									\
-	DRM_DEBUG( " pcbase = 0x%08lx  vcbase = %p\n", pcbase, vcbase );\
-	dev_priv->warp_pipe_phys[where] = pcbase;			\
-	memcpy( vcbase, which, sizeof(which) );				\
-	pcbase += WARP_UCODE_SIZE( which );				\
-	vcbase += WARP_UCODE_SIZE( which );				\
-} while (0)
-
-
-static unsigned int mga_warp_g400_microcode_size( drm_mga_private_t *dev_priv )
-{
-	unsigned int size;
-
-	size = ( WARP_UCODE_SIZE( warp_g400_tgz ) +
-		 WARP_UCODE_SIZE( warp_g400_tgza ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_tgzsf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gz ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gza ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzs ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsa ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsaf ) +
-		 WARP_UCODE_SIZE( warp_g400_t2gzsf ) );
-
-	size = PAGE_ALIGN( size );
-
-	DRM_DEBUG( "G400 ucode size = %d bytes\n", size );
-	return size;
-}
-
-static unsigned int mga_warp_g200_microcode_size( drm_mga_private_t *dev_priv )
-{
-	unsigned int size;
-
-	size = ( WARP_UCODE_SIZE( warp_g200_tgz ) +
-		 WARP_UCODE_SIZE( warp_g200_tgza ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzs ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsa ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsaf ) +
-		 WARP_UCODE_SIZE( warp_g200_tgzsf ) );
-
-	size = PAGE_ALIGN( size );
-
-	DRM_DEBUG( "G200 ucode size = %d bytes\n", size );
-	return size;
-}
-
-static int mga_warp_install_g400_microcode( drm_mga_private_t *dev_priv )
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-	unsigned int size;
-
-	size = mga_warp_g400_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
-		DRM_OS_RETURN(ENOMEM);
-	}
-
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
-
-	WARP_UCODE_INSTALL( warp_g400_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g400_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g400_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g400_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g400_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g400_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g400_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g400_tgzsaf,	MGA_WARP_TGZSAF );
-
-	WARP_UCODE_INSTALL( warp_g400_t2gz,	MGA_WARP_T2GZ );
-	WARP_UCODE_INSTALL( warp_g400_t2gzf,	MGA_WARP_T2GZF );
-	WARP_UCODE_INSTALL( warp_g400_t2gza,	MGA_WARP_T2GZA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzaf,	MGA_WARP_T2GZAF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzs,	MGA_WARP_T2GZS );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsf,	MGA_WARP_T2GZSF );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsa,	MGA_WARP_T2GZSA );
-	WARP_UCODE_INSTALL( warp_g400_t2gzsaf,	MGA_WARP_T2GZSAF );
-
-	return 0;
-}
-
-static int mga_warp_install_g200_microcode( drm_mga_private_t *dev_priv )
-{
-	unsigned char *vcbase = dev_priv->warp->handle;
-	unsigned long pcbase = dev_priv->warp->offset;
-	unsigned int size;
-
-	size = mga_warp_g200_microcode_size( dev_priv );
-	if ( size > dev_priv->warp->size ) {
-		DRM_ERROR( "microcode too large! (%u > %lu)\n",
-			   size, dev_priv->warp->size );
-		DRM_OS_RETURN(ENOMEM);
-	}
-
-	memset( dev_priv->warp_pipe_phys, 0,
-		sizeof(dev_priv->warp_pipe_phys) );
-
-	WARP_UCODE_INSTALL( warp_g200_tgz,	MGA_WARP_TGZ );
-	WARP_UCODE_INSTALL( warp_g200_tgzf,	MGA_WARP_TGZF );
-	WARP_UCODE_INSTALL( warp_g200_tgza,	MGA_WARP_TGZA );
-	WARP_UCODE_INSTALL( warp_g200_tgzaf,	MGA_WARP_TGZAF );
-	WARP_UCODE_INSTALL( warp_g200_tgzs,	MGA_WARP_TGZS );
-	WARP_UCODE_INSTALL( warp_g200_tgzsf,	MGA_WARP_TGZSF );
-	WARP_UCODE_INSTALL( warp_g200_tgzsa,	MGA_WARP_TGZSA );
-	WARP_UCODE_INSTALL( warp_g200_tgzsaf,	MGA_WARP_TGZSAF );
-
-	return 0;
-}
-
-int mga_warp_install_microcode(	drm_mga_private_t *dev_priv )
-{
-	switch ( dev_priv->chipset ) {
-	case MGA_CARD_TYPE_G400:
-		return mga_warp_install_g400_microcode( dev_priv );
-	case MGA_CARD_TYPE_G200:
-		return mga_warp_install_g200_microcode( dev_priv );
-	default:
-		DRM_OS_RETURN(EINVAL);
-	}
-}
-
-#define WMISC_EXPECTED		(MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
-
-int mga_warp_init( drm_mga_private_t *dev_priv )
-{
-	u32 wmisc;
-
-	/* FIXME: Get rid of these damned magic numbers...
-	 */
-	switch ( dev_priv->chipset ) {
-	case MGA_CARD_TYPE_G400:
-		MGA_WRITE( MGA_WIADDR2, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x00000E00 );
-		MGA_WRITE( MGA_WVRTXSZ, 0x00001807 );
-		MGA_WRITE( MGA_WACCEPTSEQ, 0x18000000 );
-		break;
-	case MGA_CARD_TYPE_G200:
-		MGA_WRITE( MGA_WIADDR, MGA_WMODE_SUSPEND );
-		MGA_WRITE( MGA_WGETMSB, 0x1606 );
-		MGA_WRITE( MGA_WVRTXSZ, 7 );
-		break;
-	default:
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	MGA_WRITE( MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
-			       MGA_WMASTER_ENABLE |
-			       MGA_WCACHEFLUSH_ENABLE) );
-	wmisc = MGA_READ( MGA_WMISC );
-	if ( wmisc != WMISC_EXPECTED ) {
-		DRM_ERROR( "WARP engine config failed! 0x%x != 0x%x\n",
-			   wmisc, WMISC_EXPECTED );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	return 0;
-}
diff --git a/bsd/r128/r128_cce.c b/bsd/r128/r128_cce.c
deleted file mode 100644
index 36cc3120..00000000
--- a/bsd/r128/r128_cce.c
+++ /dev/null
@@ -1,1024 +0,0 @@
-/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
- * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#define __NO_VERSION__
-#include "r128.h"
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-
-
-#define R128_FIFO_DEBUG		0
-
-int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
-
-/* CCE microcode (from ATI) */
-static u32 r128_cce_microcode[] = {
-	0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
-	1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
-	599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
-	11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
-	262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
-	1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
-	30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
-	1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
-	15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
-	12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
-	46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
-	459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
-	18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
-	15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
-	268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
-	15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
-	1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
-	3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
-	1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
-	15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
-	180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
-	114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
-	33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
-	1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
-	14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
-	1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
-	198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
-	114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
-	1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
-	1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
-	16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
-	174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
-	33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
-	33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
-	409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-
-int R128_READ_PLL(drm_device_t *dev, int addr)
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-
-	R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
-	return R128_READ(R128_CLOCK_CNTL_DATA);
-}
-
-#if R128_FIFO_DEBUG
-static void r128_status( drm_r128_private_t *dev_priv )
-{
-	printk( "GUI_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_GUI_STAT ) );
-	printk( "PM4_STAT           = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_STAT ) );
-	printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
-	printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
-	printk( "PM4_MICRO_CNTL     = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
-	printk( "PM4_BUFFER_CNTL    = 0x%08x\n",
-		(unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
-}
-#endif
-
-
-/* ================================================================
- * Engine, FIFO control
- */
-
-static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
-{
-	u32 tmp;
-	int i;
-
-	tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
-	R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
-			return 0;
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
-		if ( slots >= entries ) return 0;
-		DRM_OS_DELAY( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
-{
-	int i, ret;
-
-	ret = r128_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret ) return ret;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
-			r128_do_pixcache_flush( dev_priv );
-			return 0;
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "%s failed!\n", __FUNCTION__ );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-
-/* ================================================================
- * CCE control, initialization
- */
-
-/* Load the microcode for the CCE */
-static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
-{
-	int i;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	r128_do_wait_for_idle( dev_priv );
-
-	R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
-	for ( i = 0 ; i < 256 ; i++ ) {
-		R128_WRITE( R128_PM4_MICROCODE_DATAH,
-			    r128_cce_microcode[i * 2] );
-		R128_WRITE( R128_PM4_MICROCODE_DATAL,
-			    r128_cce_microcode[i * 2 + 1] );
-	}
-}
-
-/* Flush any pending commands to the CCE.  This should only be used just
- * prior to a wait for idle, as it informs the engine that the command
- * stream is ending.
- */
-static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
-{
-	u32 tmp;
-
-	tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
-}
-
-/* Wait for the CCE to go idle.
- */
-int r128_do_cce_idle( drm_r128_private_t *dev_priv )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
-			int pm4stat = R128_READ( R128_PM4_STAT );
-			if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
-			       dev_priv->cce_fifo_size ) &&
-			     !(pm4stat & (R128_PM4_BUSY |
-					  R128_PM4_GUI_ACTIVE)) ) {
-				return r128_do_pixcache_flush( dev_priv );
-			}
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if R128_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	r128_status( dev_priv );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-/* Start the Concurrent Command Engine.
- */
-static void r128_do_cce_start( drm_r128_private_t *dev_priv )
-{
-	r128_do_wait_for_idle( dev_priv );
-
-	R128_WRITE( R128_PM4_BUFFER_CNTL,
-		    dev_priv->cce_mode | dev_priv->ring.size_l2qw );
-	R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
-	R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
-
-	dev_priv->cce_running = 1;
-}
-
-/* Reset the Concurrent Command Engine.  This will not flush any pending
- * commands, so you must wait for the CCE command stream to complete
- * before calling this routine.
- */
-static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
-{
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
-	SET_RING_HEAD( &dev_priv->ring, 0 );
-	dev_priv->ring.tail = 0;
-}
-
-/* Stop the Concurrent Command Engine.  This will not flush any pending
- * commands, so you must flush the command stream and wait for the CCE
- * to go idle before calling this routine.
- */
-static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
-{
-	R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
-	R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
-
-	dev_priv->cce_running = 0;
-}
-
-/* Reset the engine.  This will stop the CCE if it is running.
- */
-static int r128_do_engine_reset( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
-
-	r128_do_pixcache_flush( dev_priv );
-
-	clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
-	mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
-
-	R128_WRITE_PLL( R128_MCLK_CNTL,
-			mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
-
-	gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
-
-	/* Taken from the sample code - do not change */
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl | R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
-	R128_WRITE( R128_GEN_RESET_CNTL,
-		    gen_reset_cntl & ~R128_SOFT_RESET_GUI );
-	R128_READ( R128_GEN_RESET_CNTL );
-
-	R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
-	R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
-	R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
-
-	/* Reset the CCE ring */
-	r128_do_cce_reset( dev_priv );
-
-	/* The CCE is no longer running after an engine reset */
-	dev_priv->cce_running = 0;
-
-	/* Reset any pending vertex, indirect buffers */
-	r128_freelist_reset( dev );
-
-	return 0;
-}
-
-static void r128_cce_init_ring_buffer( drm_device_t *dev,
-				       drm_r128_private_t *dev_priv )
-{
-	u32 ring_start;
-	u32 tmp;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The manual (p. 2) says this address is in "VM space".  This
-	 * means it's an offset from the start of AGP space.
-	 */
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		ring_start = dev_priv->cce_ring->offset - dev->agp->base;
-	else
-#endif
-		ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
-
-	R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
-
-	R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
-	R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
-
-	/* DL_RPTR_ADDR is a physical address in AGP space. */
-	SET_RING_HEAD( &dev_priv->ring, 0 );
-
-#if __REALLY_HAVE_SG
-	if ( !dev_priv->is_pci ) {
-#endif
-		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
-			    dev_priv->ring_rptr->offset );
-#if __REALLY_HAVE_SG
-	} else {
-		drm_sg_mem_t *entry = dev->sg;
-		unsigned long tmp_ofs, page_ofs;
-
-		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
-		page_ofs = tmp_ofs >> PAGE_SHIFT;
-
-		R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
-     			    entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
-			   entry->busaddr[page_ofs],
-     			   entry->handle + tmp_ofs );
-	}
-#endif
-
-	/* Set watermark control */
-	R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
-		    ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
-		    | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
-		    | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
-		    | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
-
-	/* Force read.  Why?  Because it's in the examples... */
-	R128_READ( R128_PM4_BUFFER_ADDR );
-
-	/* Turn on bus mastering */
-	tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
-	R128_WRITE( R128_BUS_CNTL, tmp );
-}
-
-static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
-{
-	drm_r128_private_t *dev_priv;
-	drm_map_list_entry_t *listentry;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
-		DRM_OS_RETURN( ENOMEM );
-
-	memset( dev_priv, 0, sizeof(drm_r128_private_t) );
-
-	dev_priv->is_pci = init->is_pci;
-
-	if ( dev_priv->is_pci && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	dev_priv->cce_mode = init->cce_mode;
-
-	/* GH: Simple idle check.
-	 */
-	atomic_set( &dev_priv->idle_count, 0 );
-
-	/* We don't support anything other than bus-mastering ring mode,
-	 * but the ring can be in either AGP or PCI space for the ring
-	 * read pointer.
-	 */
-	if ( ( init->cce_mode != R128_PM4_192BM ) &&
-	     ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
-	     ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
-		DRM_DEBUG( "Bad cce_mode!\n" );
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	switch ( init->cce_mode ) {
-	case R128_PM4_NONPM4:
-		dev_priv->cce_fifo_size = 0;
-		break;
-	case R128_PM4_192PIO:
-	case R128_PM4_192BM:
-		dev_priv->cce_fifo_size = 192;
-		break;
-	case R128_PM4_128PIO_64INDBM:
-	case R128_PM4_128BM_64INDBM:
-		dev_priv->cce_fifo_size = 128;
-		break;
-	case R128_PM4_64PIO_128INDBM:
-	case R128_PM4_64BM_128INDBM:
-	case R128_PM4_64PIO_64VCBM_64INDBM:
-	case R128_PM4_64BM_64VCBM_64INDBM:
-	case R128_PM4_64PIO_64VCPIO_64INDPIO:
-		dev_priv->cce_fifo_size = 64;
-		break;
-	}
-
-	switch ( init->fb_bpp ) {
-	case 16:
-		dev_priv->color_fmt = R128_DATATYPE_RGB565;
-		break;
-	case 32:
-	default:
-		dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
-		break;
-	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	switch ( init->depth_bpp ) {
-	case 16:
-		dev_priv->depth_fmt = R128_DATATYPE_RGB565;
-		break;
-	case 24:
-	case 32:
-	default:
-		dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
-		break;
-	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-	dev_priv->span_offset	= init->span_offset;
-
-	dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
-					  (dev_priv->front_offset >> 5));
-	dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
-					 (dev_priv->back_offset >> 5));
-	dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
-					  (dev_priv->depth_offset >> 5) |
-					  R128_DST_TILE);
-	dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
-					 (dev_priv->span_offset >> 5));
-
-	TAILQ_FOREACH(listentry, dev->maplist, link) {
-		drm_map_t *map = listentry->map;
-		if (map->type == _DRM_SHM &&
-			map->flags & _DRM_CONTAINS_LOCK) {
-			dev_priv->sarea = map;
-			break;
-		}
-	}
-
-	if(!dev_priv->sarea) {
-		DRM_ERROR("could not find sarea!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR("could not find framebuffer!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR("could not find mmio region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
-	if(!dev_priv->cce_ring) {
-		DRM_ERROR("could not find cce ring region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
-	if(!dev_priv->ring_rptr) {
-		DRM_ERROR("could not find ring read pointer!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR("could not find dma buffer region!\n");
-		dev->dev_private = (void *)dev_priv;
-		r128_do_cleanup_cce( dev );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	if ( !dev_priv->is_pci ) {
-		DRM_FIND_MAP( dev_priv->agp_textures,
-			      init->agp_textures_offset );
-		if(!dev_priv->agp_textures) {
-			DRM_ERROR("could not find agp texture region!\n");
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			DRM_OS_RETURN(EINVAL);
-		}
-	}
-
-	dev_priv->sarea_priv =
-		(drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				     init->sarea_priv_offset);
-
-	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cce_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
-		if(!dev_priv->cce_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev_priv->buffers->handle) {
-			DRM_ERROR("Could not ioremap agp regions!\n");
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			DRM_OS_RETURN(ENOMEM);
-		}
-	} else {
-		dev_priv->cce_ring->handle =
-			(void *)dev_priv->cce_ring->offset;
-		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
-	}
-
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		dev_priv->cce_buffers_offset = dev->agp->base;
-	else
-#endif
-		dev_priv->cce_buffers_offset = dev->sg->handle;
-
-	dev_priv->ring.head = ((__volatile__ u32 *)
-			       dev_priv->ring_rptr->handle);
-
-	dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
-			      + init->ring_size / sizeof(u32));
-	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
-
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
-
-	dev_priv->ring.high_mark = 128;
-
-	dev_priv->sarea_priv->last_frame = 0;
-	R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
-
-	dev_priv->sarea_priv->last_dispatch = 0;
-	R128_WRITE( R128_LAST_DISPATCH_REG,
-		    dev_priv->sarea_priv->last_dispatch );
-
-#if __REALLY_HAVE_SG
-	if ( dev_priv->is_pci ) {
-		if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
-     					    &dev_priv->bus_pci_gart) ) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
-			dev->dev_private = (void *)dev_priv;
-			r128_do_cleanup_cce( dev );
-			DRM_OS_RETURN(ENOMEM);
-		}
-		R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
-	}
-#endif
-
-	r128_cce_init_ring_buffer( dev, dev_priv );
-	r128_cce_load_microcode( dev_priv );
-
-	dev->dev_private = (void *)dev_priv;
-
-	r128_do_engine_reset( dev );
-
-	return 0;
-}
-
-int r128_do_cleanup_cce( drm_device_t *dev )
-{
-	if ( dev->dev_private ) {
-		drm_r128_private_t *dev_priv = dev->dev_private;
-
-#if __REALLY_HAVE_SG
-		if ( !dev_priv->is_pci ) {
-#endif
-			DRM_IOREMAPFREE( dev_priv->cce_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
-#if __REALLY_HAVE_SG
-		} else {
-			if (!DRM(ati_pcigart_cleanup)( dev,
-						dev_priv->phys_pci_gart,
-						dev_priv->bus_pci_gart ))
-				DRM_ERROR( "failed to cleanup PCI GART!\n" );
-		}
-#endif
-
-		DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int r128_cce_init( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_init_t init;
-
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	DRM_OS_KRNFROMUSR( init, (drm_r128_init_t *)data, sizeof(init) );
-
-	switch ( init.func ) {
-	case R128_INIT_CCE:
-		return r128_do_init_cce( dev, &init );
-	case R128_CLEANUP_CCE:
-		return r128_do_cleanup_cce( dev );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-int r128_cce_start( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
-		DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
-		return 0;
-	}
-
-	r128_do_cce_start( dev_priv );
-
-	return 0;
-}
-
-/* Stop the CCE.  The engine must have been idled before calling this
- * routine.
- */
-int r128_cce_stop( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_cce_stop_t stop;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) );
-
-	/* Flush any pending CCE commands.  This ensures any outstanding
-	 * commands are exectuted by the engine before we turn it off.
-	 */
-	if ( stop.flush ) {
-		r128_do_cce_flush( dev_priv );
-	}
-
-	/* If we fail to make the engine go idle, we return an error
-	 * code so that the DRM ioctl wrapper can try again.
-	 */
-	if ( stop.idle ) {
-		ret = r128_do_cce_idle( dev_priv );
-		if ( ret ) return ret;
-	}
-
-	/* Finally, we can turn off the CCE.  If the engine isn't idle,
-	 * we will get some dropped triangles as they won't be fully
-	 * rendered before the CCE is shut down.
-	 */
-	r128_do_cce_stop( dev_priv );
-
-	/* Reset the engine */
-	r128_do_engine_reset( dev );
-
-	return 0;
-}
-
-/* Just reset the CCE ring.  Called as part of an X Server engine reset.
- */
-int r128_cce_reset( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	r128_do_cce_reset( dev_priv );
-
-	/* The CCE is no longer running after an engine reset */
-	dev_priv->cce_running = 0;
-
-	return 0;
-}
-
-int r128_cce_idle( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cce_running ) {
-		r128_do_cce_flush( dev_priv );
-	}
-
-	return r128_do_cce_idle( dev_priv );
-}
-
-int r128_engine_reset( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return r128_do_engine_reset( dev );
-}
-
-
-/* ================================================================
- * Fullscreen mode
- */
-
-static int r128_do_init_pageflip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv->crtc_offset =      R128_READ( R128_CRTC_OFFSET );
-	dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
-
-	R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL,
-		    dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
-
-	dev_priv->page_flipping = 1;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int r128_do_cleanup_pageflip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	R128_WRITE( R128_CRTC_OFFSET,      dev_priv->crtc_offset );
-	R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
-
-	dev_priv->page_flipping = 0;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int r128_fullscreen( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_fullscreen_t fs;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) );
-
-	switch ( fs.func ) {
-	case R128_INIT_FULLSCREEN:
-		return r128_do_init_pageflip( dev );
-	case R128_CLEANUP_FULLSCREEN:
-		return r128_do_cleanup_pageflip( dev );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-
-/* ================================================================
- * Freelist management
- */
-#define R128_BUFFER_USED	0xffffffff
-#define R128_BUFFER_FREE	0
-
-#if 0
-static int r128_freelist_init( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_freelist_t *entry;
-	int i;
-
-	dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
-		DRM_OS_RETURN( ENOMEM );
-
-	memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
-	dev_priv->head->age = R128_BUFFER_USED;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-
-		entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( !entry ) DRM_OS_RETURN( ENOMEM );
-
-		entry->age = R128_BUFFER_FREE;
-		entry->buf = buf;
-		entry->prev = dev_priv->head;
-		entry->next = dev_priv->head->next;
-		if ( !entry->next )
-			dev_priv->tail = entry;
-
-		buf_priv->discard = 0;
-		buf_priv->dispatched = 0;
-		buf_priv->list_entry = entry;
-
-		dev_priv->head->next = entry;
-
-		if ( dev_priv->head->next )
-			dev_priv->head->next->prev = entry;
-	}
-
-	return 0;
-
-}
-#endif
-
-drm_buf_t *r128_freelist_get( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_buf_t *buf;
-	int i, t;
-
-	/* FIXME: Optimize -- use freelist code */
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-		if ( buf->pid == 0 )
-			return buf;
-	}
-
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-		u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
-
-		for ( i = 0 ; i < dma->buf_count ; i++ ) {
-			buf = dma->buflist[i];
-			buf_priv = buf->dev_private;
-			if ( buf->pending && buf_priv->age <= done_age ) {
-				/* The buffer has been processed, so it
-				 * can now be used.
-				 */
-				buf->pending = 0;
-				return buf;
-			}
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-	DRM_ERROR( "returning NULL!\n" );
-	return NULL;
-}
-
-void r128_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	int i;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		drm_buf_t *buf = dma->buflist[i];
-		drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-		buf_priv->age = 0;
-	}
-}
-
-
-/* ================================================================
- * CCE command submission
- */
-
-int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
-{
-	drm_r128_ring_buffer_t *ring = &dev_priv->ring;
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		r128_update_ring_snapshot( ring );
-		if ( ring->space >= n )
-			return 0;
-		DRM_OS_DELAY( 1 );
-	}
-
-	/* FIXME: This is being ignored... */
-	DRM_ERROR( "failed!\n" );
-	DRM_OS_RETURN( EBUSY );
-}
-
-static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d)
-{
-	int i;
-	drm_buf_t *buf;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = r128_freelist_get( dev );
-		if ( !buf ) DRM_OS_RETURN( EAGAIN );
-
-		buf->pid = DRM_OS_CURRENTPID;
-
-		 if ( DRM_OS_COPYTOUSR( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
-			DRM_OS_RETURN( EFAULT );
-		 if ( DRM_OS_COPYTOUSR( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
-			DRM_OS_RETURN( EFAULT );
-		d->granted_count++;
-	}
-	return 0;
-}
-
-int r128_cce_buffers( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-	int ret = 0;
-	drm_dma_t d;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) );
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_OS_CURRENTPID, d.send_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			  DRM_OS_CURRENTPID, d.request_count, dma->buf_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		ret = r128_cce_get_buffers( dev, &d );
-	}
-
-	DRM_OS_KRNTOUSR((drm_dma_t *) data, d, sizeof(d) );
-
-	return ret;
-}
diff --git a/bsd/r128/r128_drv.c b/bsd/r128/r128_drv.c
deleted file mode 100644
index cf59aa0d..00000000
--- a/bsd/r128/r128_drv.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/* r128_drv.c -- ATI Rage 128 driver -*- linux-c -*-
- * Created: Mon Dec 13 09:47:27 1999 by faith@precisioninsight.com
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Rickard E. (Rik) Faith <faith@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-
-#include <sys/types.h>
-#include <sys/bus.h>
-#include <pci/pcivar.h>
-#include <opt_drm_linux.h>
-
-#include "r128.h"
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-#if __REALLY_HAVE_SG
-#include "ati_pcigart.h"
-#endif
-
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"r128"
-#define DRIVER_DESC		"ATI Rage 128"
-#define DRIVER_DATE		"20010405"
-
-#define DRIVER_MAJOR		2
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-
-/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
- * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here.
- */
-drm_chipinfo_t DRM(devicelist)[] = {
-	{0x1002, 0x4c45, 1, "ATI Rage 128 Mobility LE"},
-	{0x1002, 0x4c46, 1, "ATI Rage 128 Mobility LF"},
-	{0x1002, 0x4d46, 1, "ATI Rage 128 Mobility MF (AGP 4x)"},
-	{0x1002, 0x4d4c, 1, "ATI Rage 128 Mobility ML"},
-	{0x1002, 0x5041, 0, "ATI Rage 128 Pro PA (PCI)"},
-	{0x1002, 0x5042, 1, "ATI Rage 128 Pro PB (AGP 2x)"},
-	{0x1002, 0x5043, 1, "ATI Rage 128 Pro PC (AGP 4x)"},
-	{0x1002, 0x5044, 0, "ATI Rage 128 Pro PD (PCI)"},
-	{0x1002, 0x5045, 1, "ATI Rage 128 Pro PE (AGP 2x)"},
-	{0x1002, 0x5046, 1, "ATI Rage 128 Pro PF (AGP 4x)"},
-	{0x1002, 0x5047, 0, "ATI Rage 128 Pro PG (PCI)"},
-	{0x1002, 0x5048, 1, "ATI Rage 128 Pro PH (AGP)"},
-	{0x1002, 0x5049, 1, "ATI Rage 128 Pro PI (AGP)"},
-	{0x1002, 0x504a, 0, "ATI Rage 128 Pro PJ (PCI)"},
-	{0x1002, 0x504b, 1, "ATI Rage 128 Pro PK (AGP)"},
-	{0x1002, 0x504c, 1, "ATI Rage 128 Pro PL (AGP)"},
-	{0x1002, 0x504d, 0, "ATI Rage 128 Pro PM (PCI)"},
-	{0x1002, 0x504e, 1, "ATI Rage 128 Pro PN (AGP)"},
-	{0x1002, 0x505f, 1, "ATI Rage 128 Pro PO (AGP)"},
-	{0x1002, 0x5050, 0, "ATI Rage 128 Pro PP (PCI)"},
-	{0x1002, 0x5051, 1, "ATI Rage 128 Pro PQ (AGP)"},
-	{0x1002, 0x5052, 1, "ATI Rage 128 Pro PR (AGP)"},
-	{0x1002, 0x5053, 0, "ATI Rage 128 Pro PS (PCI)"},
-	{0x1002, 0x5054, 1, "ATI Rage 128 Pro PT (AGP)"},
-	{0x1002, 0x5055, 1, "ATI Rage 128 Pro PU (AGP)"},
-	{0x1002, 0x5056, 0, "ATI Rage 128 Pro PV (PCI)"},
-	{0x1002, 0x5057, 1, "ATI Rage 128 Pro PW (AGP)"},
-	{0x1002, 0x5058, 1, "ATI Rage 128 Pro PX (AGP)"},
-	{0x1002, 0x5245, 0, "ATI Rage 128 GL (PCI)"},
-	{0x1002, 0x5246, 1, "ATI Rage 128 GL (AGP 2x)"},
-	{0x1002, 0x524b, 0, "ATI Rage 128 VR (PCI)"},
-	{0x1002, 0x524c, 1, "ATI Rage 128 VR (AGP 2x)"},
-	{0x1002, 0x5345, 0, "ATI Rage 128 SE (PCI)"},
-	{0x1002, 0x5346, 1, "ATI Rage 128 SF (AGP 2x)"},
-	{0x1002, 0x5347, 1, "ATI Rage 128 SG (AGP 4x)"},
-	{0x1002, 0x5348, 0, "ATI Rage 128 SH (unknown)"},
-	{0x1002, 0x534b, 0, "ATI Rage 128 SK (PCI)"},
-	{0x1002, 0x534c, 1, "ATI Rage 128 SL (AGP 2x)"},
-	{0x1002, 0x534d, 1, "ATI Rage 128 SM (AGP 4x)"},
-	{0x1002, 0x534e, 1, "ATI Rage 128 (AGP 4x?)"},
-	{0, 0, 0, NULL}
-};
-
-#define DRIVER_IOCTLS							    \
-   [DRM_IOCTL_NR(DRM_IOCTL_DMA)]             = { r128_cce_buffers,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INIT)]       = { r128_cce_init,     1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_START)]  = { r128_cce_start,    1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_STOP)]   = { r128_cce_stop,     1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_RESET)]  = { r128_cce_reset,    1, 1 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CCE_IDLE)]   = { r128_cce_idle,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_RESET)]      = { r128_engine_reset, 1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_FULLSCREEN)] = { r128_fullscreen,   1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_SWAP)]       = { r128_cce_swap,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_CLEAR)]      = { r128_cce_clear,    1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_VERTEX)]     = { r128_cce_vertex,   1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INDICES)]    = { r128_cce_indices,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_BLIT)]       = { r128_cce_blit,     1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_DEPTH)]      = { r128_cce_depth,    1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_STIPPLE)]    = { r128_cce_stipple,  1, 0 }, \
-   [DRM_IOCTL_NR(DRM_IOCTL_R128_INDIRECT)]   = { r128_cce_indirect, 1, 1 },
-
-
-#if 0
-/* GH: Count data sent to card via ring or vertex/indirect buffers.
- */
-#define __HAVE_COUNTERS         3
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#endif
-
-
-#include "drm_agpsupport.h"
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lock.h"
-#include "drm_memory.h"
-#include "drm_sysctl.h"
-#include "drm_vm.h"
-#if __REALLY_HAVE_SG
-#include "drm_scatter.h"
-#endif
-
-DRIVER_MODULE(r128, pci, r128_driver, r128_devclass, 0, 0);
diff --git a/bsd/r128/r128_state.c b/bsd/r128/r128_state.c
deleted file mode 100644
index 34500bb3..00000000
--- a/bsd/r128/r128_state.c
+++ /dev/null
@@ -1,1572 +0,0 @@
-/* r128_state.c -- State support for r128 -*- linux-c -*-
- * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-
-#include "r128.h"
-#include "drmP.h"
-#include "drm.h"
-#include "r128_drm.h"
-#include "r128_drv.h"
-#include "drm.h"
-
-
-
-/* ================================================================
- * CCE hardware state programming functions
- */
-
-static void r128_emit_clip_rects( drm_r128_private_t *dev_priv,
-				  drm_clip_rect_t *boxes, int count )
-{
-	u32 aux_sc_cntl = 0x00000000;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 17 );
-
-	if ( count >= 1 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX1_SC_LEFT, 3 ) );
-		OUT_RING( boxes[0].x1 );
-		OUT_RING( boxes[0].x2 - 1 );
-		OUT_RING( boxes[0].y1 );
-		OUT_RING( boxes[0].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR);
-	}
-	if ( count >= 2 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX2_SC_LEFT, 3 ) );
-		OUT_RING( boxes[1].x1 );
-		OUT_RING( boxes[1].x2 - 1 );
-		OUT_RING( boxes[1].y1 );
-		OUT_RING( boxes[1].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR);
-	}
-	if ( count >= 3 ) {
-		OUT_RING( CCE_PACKET0( R128_AUX3_SC_LEFT, 3 ) );
-		OUT_RING( boxes[2].x1 );
-		OUT_RING( boxes[2].x2 - 1 );
-		OUT_RING( boxes[2].y1 );
-		OUT_RING( boxes[2].y2 - 1 );
-
-		aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR);
-	}
-
-	OUT_RING( CCE_PACKET0( R128_AUX_SC_CNTL, 0 ) );
-	OUT_RING( aux_sc_cntl );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_core( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_SCALE_3D_CNTL, 0 ) );
-	OUT_RING( ctx->scale_3d_cntl );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_context( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 13 );
-
-	OUT_RING( CCE_PACKET0( R128_DST_PITCH_OFFSET_C, 11 ) );
-	OUT_RING( ctx->dst_pitch_offset_c );
-	OUT_RING( ctx->dp_gui_master_cntl_c );
-	OUT_RING( ctx->sc_top_left_c );
-	OUT_RING( ctx->sc_bottom_right_c );
-	OUT_RING( ctx->z_offset_c );
-	OUT_RING( ctx->z_pitch_c );
-	OUT_RING( ctx->z_sten_cntl_c );
-	OUT_RING( ctx->tex_cntl_c );
-	OUT_RING( ctx->misc_3d_state_cntl_reg );
-	OUT_RING( ctx->texture_clr_cmp_clr_c );
-	OUT_RING( ctx->texture_clr_cmp_msk_c );
-	OUT_RING( ctx->fog_color_c );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_setup( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 3 );
-
-	OUT_RING( CCE_PACKET1( R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP ) );
-	OUT_RING( ctx->setup_cntl );
-	OUT_RING( ctx->pm4_vc_fpu_setup );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_masks( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 5 );
-
-	OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-	OUT_RING( ctx->dp_write_mask );
-
-	OUT_RING( CCE_PACKET0( R128_STEN_REF_MASK_C, 1 ) );
-	OUT_RING( ctx->sten_ref_mask_c );
-	OUT_RING( ctx->plane_3d_mask_c );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_window( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_WINDOW_XY_OFFSET, 0 ) );
-	OUT_RING( ctx->window_xy_offset );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_tex0( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
-	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 7 + R128_MAX_TEXTURE_LEVELS );
-
-	OUT_RING( CCE_PACKET0( R128_PRIM_TEX_CNTL_C,
-			       2 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	OUT_RING( ctx->tex_size_pitch_c );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
-
-	OUT_RING( CCE_PACKET0( R128_CONSTANT_COLOR_C, 1 ) );
-	OUT_RING( ctx->constant_color_c );
-	OUT_RING( tex->tex_border_color );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_tex1( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 5 + R128_MAX_TEXTURE_LEVELS );
-
-	OUT_RING( CCE_PACKET0( R128_SEC_TEX_CNTL_C,
-			       1 + R128_MAX_TEXTURE_LEVELS ) );
-	OUT_RING( tex->tex_cntl );
-	OUT_RING( tex->tex_combine_cntl );
-	for ( i = 0 ; i < R128_MAX_TEXTURE_LEVELS ; i++ ) {
-		OUT_RING( tex->tex_offset[i] );
-	}
-
-	OUT_RING( CCE_PACKET0( R128_SEC_TEXTURE_BORDER_COLOR_C, 0 ) );
-	OUT_RING( tex->tex_border_color );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void r128_emit_state( drm_r128_private_t *dev_priv )
-{
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	unsigned int dirty = sarea_priv->dirty;
-
-	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
-
-	if ( dirty & R128_UPLOAD_CORE ) {
-		r128_emit_core( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_CORE;
-	}
-
-	if ( dirty & R128_UPLOAD_CONTEXT ) {
-		r128_emit_context( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
-	}
-
-	if ( dirty & R128_UPLOAD_SETUP ) {
-		r128_emit_setup( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
-	}
-
-	if ( dirty & R128_UPLOAD_MASKS ) {
-		r128_emit_masks( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
-	}
-
-	if ( dirty & R128_UPLOAD_WINDOW ) {
-		r128_emit_window( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
-	}
-
-	if ( dirty & R128_UPLOAD_TEX0 ) {
-		r128_emit_tex0( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
-	}
-
-	if ( dirty & R128_UPLOAD_TEX1 ) {
-		r128_emit_tex1( dev_priv );
-		sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
-	}
-
-	/* Turn off the texture cache flushing */
-	sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
-
-	sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
-}
-
-
-#if R128_PERFORMANCE_BOXES
-/* ================================================================
- * Performance monitoring functions
- */
-
-static void r128_clear_box( drm_r128_private_t *dev_priv,
-			    int x, int y, int w, int h,
-			    int r, int g, int b )
-{
-	u32 pitch, offset;
-	u32 fb_bpp, color;
-	RING_LOCALS;
-
-	switch ( dev_priv->fb_bpp ) {
-	case 16:
-		fb_bpp = R128_GMC_DST_16BPP;
-		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
-		break;
-	case 24:
-		fb_bpp = R128_GMC_DST_24BPP;
-		color = ((r << 16) | (g << 8) | b);
-		break;
-	case 32:
-		fb_bpp = R128_GMC_DST_32BPP;
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
-		break;
-	default:
-		return;
-	}
-
-	offset = dev_priv->back_offset;
-	pitch = dev_priv->back_pitch >> 3;
-
-	BEGIN_RING( 6 );
-
-	OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_SOLID_COLOR |
-		  fb_bpp |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_P |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_AUX_CLIP_DIS );
-
-	OUT_RING( (pitch << 21) | (offset >> 5) );
-	OUT_RING( color );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_performance_boxes( drm_r128_private_t *dev_priv )
-{
-	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
-		r128_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
-	} else {
-		atomic_set( &dev_priv->idle_count, 0 );
-	}
-}
-
-#endif
-
-
-/* ================================================================
- * CCE command dispatch functions
- */
-
-static void r128_print_dirty( const char *msg, unsigned int flags )
-{
-	DRM_INFO( "%s: (0x%x) %s%s%s%s%s%s%s%s%s\n",
-		  msg,
-		  flags,
-		  (flags & R128_UPLOAD_CORE)        ? "core, " : "",
-		  (flags & R128_UPLOAD_CONTEXT)     ? "context, " : "",
-		  (flags & R128_UPLOAD_SETUP)       ? "setup, " : "",
-		  (flags & R128_UPLOAD_TEX0)        ? "tex0, " : "",
-		  (flags & R128_UPLOAD_TEX1)        ? "tex1, " : "",
-		  (flags & R128_UPLOAD_MASKS)       ? "masks, " : "",
-		  (flags & R128_UPLOAD_WINDOW)      ? "window, " : "",
-		  (flags & R128_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
-		  (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
-}
-
-static void r128_cce_dispatch_clear( drm_device_t *dev,
-				     drm_r128_clear_t *clear )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	unsigned int flags = clear->flags;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
-		unsigned int tmp = flags;
-
-		flags &= ~(R128_FRONT | R128_BACK);
-		if ( tmp & R128_FRONT ) flags |= R128_BACK;
-		if ( tmp & R128_BACK )  flags |= R128_FRONT;
-	}
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   pbox[i].x1, pbox[i].y1, pbox[i].x2,
-			   pbox[i].y2, flags );
-
-		if ( flags & (R128_FRONT | R128_BACK) ) {
-			BEGIN_RING( 2 );
-
-			OUT_RING( CCE_PACKET0( R128_DP_WRITE_MASK, 0 ) );
-			OUT_RING( clear->color_mask );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_FRONT ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
-
-			OUT_RING( dev_priv->front_pitch_offset_c );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_BACK ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS );
-
-			OUT_RING( dev_priv->back_pitch_offset_c );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & R128_DEPTH ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_AUX_CLIP_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( clear->clear_depth );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-	}
-}
-
-static void r128_cce_dispatch_swap( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-#if R128_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	r128_cce_performance_boxes( dev_priv );
-#endif
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		BEGIN_RING( 7 );
-
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_AUX_CLIP_DIS |
-			  R128_GMC_WR_MSK_DIS );
-
-		OUT_RING( dev_priv->back_pitch_offset_c );
-		OUT_RING( dev_priv->front_pitch_offset_c );
-
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
-
-		ADVANCE_RING();
-	}
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_dispatch_flip( drm_device_t *dev )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
-
-#if R128_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	r128_cce_performance_boxes( dev_priv );
-#endif
-
-	BEGIN_RING( 4 );
-
-	R128_WAIT_UNTIL_PAGE_FLIPPED();
-	OUT_RING( CCE_PACKET0( R128_CRTC_OFFSET, 0 ) );
-
-	if ( dev_priv->current_page == 0 ) {
-		OUT_RING( dev_priv->back_offset );
-		dev_priv->current_page = 1;
-	} else {
-		OUT_RING( dev_priv->front_offset );
-		dev_priv->current_page = 0;
-	}
-
-	ADVANCE_RING();
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_LAST_FRAME_REG, 0 ) );
-	OUT_RING( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-static void r128_cce_dispatch_vertex( drm_device_t *dev,
-				      drm_buf_t *buf )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int format = sarea_priv->vc_format;
-	int offset = buf->bus_address;
-	int size = buf->used;
-	int prim = buf_priv->prim;
-	int i = 0;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: buf=%d nbox=%d\n",
-		   __FUNCTION__, buf->idx, sarea_priv->nbox );
-
-	if ( 0 )
-		r128_print_dirty( "dispatch_vertex", sarea_priv->dirty );
-
-	if ( buf->used ) {
-		buf_priv->dispatched = 1;
-
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
-		}
-
-		do {
-			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
-			}
-
-			/* Emit the vertex buffer rendering commands */
-			BEGIN_RING( 5 );
-
-			OUT_RING( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-			OUT_RING( offset );
-			OUT_RING( size );
-			OUT_RING( format );
-			OUT_RING( prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST |
-				  (size << R128_CCE_VC_CNTL_NUM_SHIFT) );
-
-			ADVANCE_RING();
-
-			i += 3;
-		} while ( i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		buf->used = 0;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-
-	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
-	sarea_priv->nbox = 0;
-}
-
-static void r128_cce_dispatch_indirect( drm_device_t *dev,
-					drm_buf_t *buf,
-					int start, int end )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
-
-	if ( start != end ) {
-		int offset = buf->bus_address + start;
-		int dwords = (end - start + 3) / sizeof(u32);
-
-		/* Indirect buffer data must be an even number of
-		 * dwords, so if we've been given an odd number we must
-		 * pad the data with a Type-2 CCE packet.
-		 */
-		if ( dwords & 1 ) {
-			u32 *data = (u32 *)
-				((char *)dev_priv->buffers->handle
-				 + buf->offset + start);
-			data[dwords++] = cpu_to_le32( R128_CCE_PACKET2 );
-		}
-
-		buf_priv->dispatched = 1;
-
-		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
-
-		OUT_RING( CCE_PACKET0( R128_PM4_IW_INDOFF, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
-
-		ADVANCE_RING();
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the indirect buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		buf->used = 0;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-}
-
-static void r128_cce_dispatch_indices( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       int start, int end,
-				       int count )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_buf_priv_t *buf_priv = buf->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int format = sarea_priv->vc_format;
-	int offset = dev_priv->buffers->offset - dev_priv->cce_buffers_offset;
-	int prim = buf_priv->prim;
-	u32 *data;
-	int dwords;
-	int i = 0;
-	RING_LOCALS;
-	DRM_DEBUG( "indices: s=%d e=%d c=%d\n", start, end, count );
-
-	if ( 0 )
-		r128_print_dirty( "dispatch_indices", sarea_priv->dirty );
-
-	if ( start != end ) {
-		buf_priv->dispatched = 1;
-
-		if ( sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS ) {
-			r128_emit_state( dev_priv );
-		}
-
-		dwords = (end - start + 3) / sizeof(u32);
-
-		data = (u32 *)((char *)dev_priv->buffers->handle
-			       + buf->offset + start);
-
-		data[0] = cpu_to_le32( CCE_PACKET3( R128_3D_RNDR_GEN_INDX_PRIM,
-						    dwords-2 ) );
-
-		data[1] = cpu_to_le32( offset );
-		data[2] = cpu_to_le32( R128_MAX_VB_VERTS );
-		data[3] = cpu_to_le32( format );
-		data[4] = cpu_to_le32( (prim | R128_CCE_VC_CNTL_PRIM_WALK_IND |
-					(count << 16)) );
-
-		if ( count & 0x1 ) {
-#if BYTE_ORDER==LITTLE_ENDIAN
-			data[dwords-1] &= 0x0000ffff;
-#else
-			data[dwords-1] &= 0xffff0000;
-#endif
-		}
-
-		do {
-			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				r128_emit_clip_rects( dev_priv,
-						      &sarea_priv->boxes[i],
-						      sarea_priv->nbox - i );
-			}
-
-			r128_cce_dispatch_indirect( dev, buf, start, end );
-
-			i += 3;
-		} while ( i < sarea_priv->nbox );
-	}
-
-	if ( buf_priv->discard ) {
-		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-		/* Emit the vertex buffer age */
-		BEGIN_RING( 2 );
-
-		OUT_RING( CCE_PACKET0( R128_LAST_DISPATCH_REG, 0 ) );
-		OUT_RING( buf_priv->age );
-
-		ADVANCE_RING();
-
-		buf->pending = 1;
-		/* FIXME: Check dispatched field */
-		buf_priv->dispatched = 0;
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-
-	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
-	sarea_priv->nbox = 0;
-}
-
-static int r128_cce_dispatch_blit( drm_device_t *dev,
-				   drm_r128_blit_t *blit, int pid )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	u32 *data;
-	int dword_shift, dwords;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	/* The compiler won't optimize away a division by a variable,
-	 * even if the only legal values are powers of two.  Thus, we'll
-	 * use a shift instead.
-	 */
-	switch ( blit->format ) {
-	case R128_DATATYPE_ARGB8888:
-		dword_shift = 0;
-		break;
-	case R128_DATATYPE_ARGB1555:
-	case R128_DATATYPE_RGB565:
-	case R128_DATATYPE_ARGB4444:
-		dword_shift = 1;
-		break;
-	case R128_DATATYPE_CI8:
-	case R128_DATATYPE_RGB8:
-		dword_shift = 2;
-		break;
-	default:
-		DRM_ERROR( "invalid blit format %d\n", blit->format );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	/* Flush the pixel cache, and mark the contents as Read Invalid.
-	 * This ensures no pixel data gets mixed up with the texture
-	 * data from the host data blit, otherwise part of the texture
-	 * image may be corrupted.
-	 */
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_RI_GUI | R128_PC_FLUSH_GUI );
-
-	ADVANCE_RING();
-
-	/* Dispatch the indirect buffer.
-	 */
-	buf = dma->buflist[blit->idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != pid ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   pid, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", blit->idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf_priv->discard = 1;
-
-	dwords = (blit->width * blit->height) >> dword_shift;
-
-	data = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
-
-	data[0] = cpu_to_le32( CCE_PACKET3( R128_CNTL_HOSTDATA_BLT, dwords + 6 ) );
-	data[1] = cpu_to_le32( (R128_GMC_DST_PITCH_OFFSET_CNTL |
-				R128_GMC_BRUSH_NONE |
-				(blit->format << 8) |
-				R128_GMC_SRC_DATATYPE_COLOR |
-				R128_ROP3_S |
-				R128_DP_SRC_SOURCE_HOST_DATA |
-				R128_GMC_CLR_CMP_CNTL_DIS |
-				R128_GMC_AUX_CLIP_DIS |
-				R128_GMC_WR_MSK_DIS) );
-
-	data[2] = cpu_to_le32( (blit->pitch << 21) | (blit->offset >> 5) );
-	data[3] = cpu_to_le32( 0xffffffff );
-	data[4] = cpu_to_le32( 0xffffffff );
-	data[5] = cpu_to_le32( (blit->y << 16) | blit->x );
-	data[6] = cpu_to_le32( (blit->height << 16) | blit->width );
-	data[7] = cpu_to_le32( dwords );
-
-	buf->used = (dwords + 8) * sizeof(u32);
-
-	r128_cce_dispatch_indirect( dev, buf, 0, buf->used );
-
-	/* Flush the pixel cache after the blit completes.  This ensures
-	 * the texture data is written out to memory before rendering
-	 * continues.
-	 */
-	BEGIN_RING( 2 );
-
-	OUT_RING( CCE_PACKET0( R128_PC_GUI_CTLSTAT, 0 ) );
-	OUT_RING( R128_PC_FLUSH_GUI );
-
-	ADVANCE_RING();
-
-	return 0;
-}
-
-
-/* ================================================================
- * Tiled depth buffer management
- *
- * FIXME: These should all set the destination write mask for when we
- * have hardware stencil support.
- */
-
-static int r128_cce_dispatch_write_span( drm_device_t *dev,
-					 drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, x, y;
-	u32 *buffer;
-	u8 *mask;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( DRM_OS_COPYFROMUSR( &x, depth->x, sizeof(x) ) ) {
-		DRM_OS_RETURN( EFAULT );
-	}
-	if ( DRM_OS_COPYFROMUSR( &y, depth->y, sizeof(y) ) ) {
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	buffer = DRM_OS_MALLOC( depth->n * sizeof(u32) );
-	if ( buffer == NULL )
-		DRM_OS_RETURN( ENOMEM );
-	if ( DRM_OS_COPYFROMUSR( buffer, depth->buffer,
-			     depth->n * sizeof(u32) ) ) {
-		DRM_OS_FREE( buffer );
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	if ( depth->mask ) {
-		mask = DRM_OS_MALLOC( depth->n * sizeof(u8) );
-		if ( mask == NULL ) {
-			DRM_OS_FREE( buffer );
-			DRM_OS_RETURN( ENOMEM );
-		}
-		if ( DRM_OS_COPYFROMUSR( mask, depth->mask,
-				     depth->n * sizeof(u8) ) ) {
-			DRM_OS_FREE( buffer );
-			DRM_OS_FREE( mask );
-			DRM_OS_RETURN( EFAULT );
-		}
-
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
-
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
-
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
-
-				OUT_RING( (x << 16) | y );
-				OUT_RING( (1 << 16) | 1 );
-
-				ADVANCE_RING();
-			}
-		}
-
-		DRM_OS_FREE( mask );
-	} else {
-		for ( i = 0 ; i < count ; i++, x++ ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (1 << 16) | 1 );
-
-			ADVANCE_RING();
-		}
-	}
-
-	DRM_OS_FREE( buffer );
-
-	return 0;
-}
-
-static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
-					   drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, *x, *y;
-	u32 *buffer;
-	u8 *mask;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-
-	x = DRM_OS_MALLOC( count * sizeof(*x) );
-	if ( x == NULL ) {
-		DRM_OS_RETURN( ENOMEM );
-	}
-	y = DRM_OS_MALLOC( count * sizeof(*y) );
-	if ( y == NULL ) {
-		DRM_OS_FREE( x );
-		DRM_OS_RETURN( ENOMEM );
-	}
-	if ( DRM_OS_COPYFROMUSR( x, depth->x, count * sizeof(int) ) ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_RETURN( EFAULT );
-	}
-	if ( DRM_OS_COPYFROMUSR( y, depth->y, count * sizeof(int) ) ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	buffer = DRM_OS_MALLOC( depth->n * sizeof(u32) );
-	if ( buffer == NULL ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_RETURN( ENOMEM );
-	}
-	if ( DRM_OS_COPYFROMUSR( buffer, depth->buffer,
-			     depth->n * sizeof(u32) ) ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_FREE( buffer );
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	if ( depth->mask ) {
-		mask = DRM_OS_MALLOC( depth->n * sizeof(u8) );
-		if ( mask == NULL ) {
-			DRM_OS_FREE( x );
-			DRM_OS_FREE( y );
-			DRM_OS_FREE( buffer );
-			DRM_OS_RETURN( ENOMEM );
-		}
-		if ( DRM_OS_COPYFROMUSR( mask, depth->mask,
-				     depth->n * sizeof(u8) ) ) {
-			DRM_OS_FREE( x );
-			DRM_OS_FREE( y );
-			DRM_OS_FREE( buffer );
-			DRM_OS_FREE( mask );
-			DRM_OS_RETURN( EFAULT );
-		}
-
-		for ( i = 0 ; i < count ; i++ ) {
-			if ( mask[i] ) {
-				BEGIN_RING( 6 );
-
-				OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-				OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-					  R128_GMC_BRUSH_SOLID_COLOR |
-					  (dev_priv->depth_fmt << 8) |
-					  R128_GMC_SRC_DATATYPE_COLOR |
-					  R128_ROP3_P |
-					  R128_GMC_CLR_CMP_CNTL_DIS |
-					  R128_GMC_WR_MSK_DIS );
-
-				OUT_RING( dev_priv->depth_pitch_offset_c );
-				OUT_RING( buffer[i] );
-
-				OUT_RING( (x[i] << 16) | y[i] );
-				OUT_RING( (1 << 16) | 1 );
-
-				ADVANCE_RING();
-			}
-		}
-
-		DRM_OS_FREE( mask );
-	} else {
-		for ( i = 0 ; i < count ; i++ ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CCE_PACKET3( R128_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( R128_GMC_DST_PITCH_OFFSET_CNTL |
-				  R128_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->depth_fmt << 8) |
-				  R128_GMC_SRC_DATATYPE_COLOR |
-				  R128_ROP3_P |
-				  R128_GMC_CLR_CMP_CNTL_DIS |
-				  R128_GMC_WR_MSK_DIS );
-
-			OUT_RING( dev_priv->depth_pitch_offset_c );
-			OUT_RING( buffer[i] );
-
-			OUT_RING( (x[i] << 16) | y[i] );
-			OUT_RING( (1 << 16) | 1 );
-
-			ADVANCE_RING();
-		}
-	}
-
-	DRM_OS_FREE( x );
-	DRM_OS_FREE( y );
-	DRM_OS_FREE( buffer );
-
-	return 0;
-}
-
-static int r128_cce_dispatch_read_span( drm_device_t *dev,
-					drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, x, y;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( DRM_OS_COPYFROMUSR( &x, depth->x, sizeof(x) ) ) {
-		DRM_OS_RETURN( EFAULT );
-	}
-	if ( DRM_OS_COPYFROMUSR( &y, depth->y, sizeof(y) ) ) {
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	BEGIN_RING( 7 );
-
-	OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-	OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-		  R128_GMC_DST_PITCH_OFFSET_CNTL |
-		  R128_GMC_BRUSH_NONE |
-		  (dev_priv->depth_fmt << 8) |
-		  R128_GMC_SRC_DATATYPE_COLOR |
-		  R128_ROP3_S |
-		  R128_DP_SRC_SOURCE_MEMORY |
-		  R128_GMC_CLR_CMP_CNTL_DIS |
-		  R128_GMC_WR_MSK_DIS );
-
-	OUT_RING( dev_priv->depth_pitch_offset_c );
-	OUT_RING( dev_priv->span_pitch_offset_c );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (0 << 16) | 0 );
-	OUT_RING( (count << 16) | 1 );
-
-	ADVANCE_RING();
-
-	return 0;
-}
-
-static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
-					  drm_r128_depth_t *depth )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int count, *x, *y;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	count = depth->n;
-	if ( count > dev_priv->depth_pitch ) {
-		count = dev_priv->depth_pitch;
-	}
-
-	x = DRM_OS_MALLOC( count * sizeof(*x) );
-	if ( x == NULL ) {
-		DRM_OS_RETURN( ENOMEM );
-	}
-	y = DRM_OS_MALLOC( count * sizeof(*y) );
-	if ( y == NULL ) {
-		DRM_OS_FREE( x );
-		DRM_OS_RETURN( ENOMEM );
-	}
-	if ( DRM_OS_COPYFROMUSR( x, depth->x, count * sizeof(int) ) ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_RETURN( EFAULT );
-	}
-	if ( DRM_OS_COPYFROMUSR( y, depth->y, count * sizeof(int) ) ) {
-		DRM_OS_FREE( x );
-		DRM_OS_FREE( y );
-		DRM_OS_RETURN( EFAULT );
-	}
-
-	for ( i = 0 ; i < count ; i++ ) {
-		BEGIN_RING( 7 );
-
-		OUT_RING( CCE_PACKET3( R128_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( R128_GMC_SRC_PITCH_OFFSET_CNTL |
-			  R128_GMC_DST_PITCH_OFFSET_CNTL |
-			  R128_GMC_BRUSH_NONE |
-			  (dev_priv->depth_fmt << 8) |
-			  R128_GMC_SRC_DATATYPE_COLOR |
-			  R128_ROP3_S |
-			  R128_DP_SRC_SOURCE_MEMORY |
-			  R128_GMC_CLR_CMP_CNTL_DIS |
-			  R128_GMC_WR_MSK_DIS );
-
-		OUT_RING( dev_priv->depth_pitch_offset_c );
-		OUT_RING( dev_priv->span_pitch_offset_c );
-
-		OUT_RING( (x[i] << 16) | y[i] );
-		OUT_RING( (i << 16) | 0 );
-		OUT_RING( (1 << 16) | 1 );
-
-		ADVANCE_RING();
-	}
-
-	DRM_OS_FREE( x );
-	DRM_OS_FREE( y );
-
-	return 0;
-}
-
-
-/* ================================================================
- * Polygon stipple
- */
-
-static void r128_cce_dispatch_stipple( drm_device_t *dev, u32 *stipple )
-{
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 33 );
-
-	OUT_RING( CCE_PACKET0( R128_BRUSH_DATA0, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
-	}
-
-	ADVANCE_RING();
-}
-
-
-/* ================================================================
- * IOCTL functions
- */
-
-int r128_cce_clear( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_r128_clear_t clear;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( clear, (drm_r128_clear_t *) data,
-			     sizeof(clear) );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
-
-	r128_cce_dispatch_clear( dev, &clear );
-
-	/* Make sure we restore the 3D state next time.
-	 */
-	dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
-
-	return 0;
-}
-
-int r128_cce_swap( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
-
-	if ( !dev_priv->page_flipping ) {
-		r128_cce_dispatch_swap( dev );
-		dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
-						R128_UPLOAD_MASKS);
-	} else {
-		r128_cce_dispatch_flip( dev );
-	}
-
-	return 0;
-}
-
-int r128_cce_vertex( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_vertex_t vertex;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_OS_KRNFROMUSR( vertex, (drm_r128_vertex_t *) data,
-			     sizeof(vertex) );
-
-	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
-		   __FUNCTION__, DRM_OS_CURRENTPID,
-		   vertex.idx, vertex.count, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf->used = vertex.count;
-	buf_priv->prim = vertex.prim;
-	buf_priv->discard = vertex.discard;
-
-	r128_cce_dispatch_vertex( dev, buf );
-
-	return 0;
-}
-
-int r128_cce_indices( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_indices_t elts;
-	int count;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_OS_KRNFROMUSR( elts, (drm_r128_indices_t *) data,
-			     sizeof(elts) );
-
-	DRM_DEBUG( "%s: pid=%d buf=%d s=%d e=%d d=%d\n",
-		   __FUNCTION__, DRM_OS_CURRENTPID,
-		   elts.idx, elts.start, elts.end, elts.discard );
-
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( elts.prim < 0 ||
-	     elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[elts.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	count = (elts.end - elts.start) / sizeof(u16);
-	elts.start -= R128_INDEX_PRIM_OFFSET;
-
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf->used = elts.end;
-	buf_priv->prim = elts.prim;
-	buf_priv->discard = elts.discard;
-
-	r128_cce_dispatch_indices( dev, buf, elts.start, elts.end, count );
-
-	return 0;
-}
-
-int r128_cce_blit( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_blit_t blit;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( blit, (drm_r128_blit_t *) data,
-			     sizeof(blit) );
-
-	DRM_DEBUG( "%s: pid=%d index=%d\n",
-		   __FUNCTION__, DRM_OS_CURRENTPID, blit.idx );
-
-	if ( blit.idx < 0 || blit.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   blit.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	return r128_cce_dispatch_blit( dev, &blit, DRM_OS_CURRENTPID );
-}
-
-int r128_cce_depth( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_depth_t depth;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( depth, (drm_r128_depth_t *) data,
-			     sizeof(depth) );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	switch ( depth.func ) {
-	case R128_WRITE_SPAN:
-		return r128_cce_dispatch_write_span( dev, &depth );
-	case R128_WRITE_PIXELS:
-		return r128_cce_dispatch_write_pixels( dev, &depth );
-	case R128_READ_SPAN:
-		return r128_cce_dispatch_read_span( dev, &depth );
-	case R128_READ_PIXELS:
-		return r128_cce_dispatch_read_pixels( dev, &depth );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-int r128_cce_stipple( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_r128_stipple_t stipple;
-	u32 mask[32];
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( stipple, (drm_r128_stipple_t *) data,
-			     sizeof(stipple) );
-
-	if ( DRM_OS_COPYFROMUSR( &mask, stipple.mask,
-			     32 * sizeof(u32) ) )
-		DRM_OS_RETURN( EFAULT );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	r128_cce_dispatch_stipple( dev, mask );
-
-	return 0;
-}
-
-int r128_cce_indirect( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_r128_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_r128_buf_priv_t *buf_priv;
-	drm_r128_indirect_t indirect;
-#if 0
-	RING_LOCALS;
-#endif
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	DRM_OS_KRNFROMUSR( indirect, (drm_r128_indirect_t *) data,
-			     sizeof(indirect) );
-
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
-
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	buf = dma->buflist[indirect.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN(EINVAL);
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf->used = indirect.end;
-	buf_priv->discard = indirect.discard;
-
-#if 0
-	/* Wait for the 3D stream to idle before the indirect buffer
-	 * containing 2D acceleration commands is processed.
-	 */
-	BEGIN_RING( 2 );
-	RADEON_WAIT_UNTIL_3D_IDLE();
-	ADVANCE_RING();
-#endif
-
-	/* Dispatch the indirect buffer full of commands from the
-	 * X server.  This is insecure and is thus only available to
-	 * privileged clients.
-	 */
-	r128_cce_dispatch_indirect( dev, buf, indirect.start, indirect.end );
-
-	return 0;
-}
diff --git a/bsd/radeon/radeon_cp.c b/bsd/radeon/radeon_cp.c
deleted file mode 100644
index 9c262ae3..00000000
--- a/bsd/radeon/radeon_cp.c
+++ /dev/null
@@ -1,1423 +0,0 @@
-/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
- *
- * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#include "radeon.h"
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-
-#include <vm/vm.h>
-#include <vm/pmap.h>
-
-#define RADEON_FIFO_DEBUG	0
-
-#if defined(__alpha__)
-# define PCIGART_ENABLED
-#else
-# undef PCIGART_ENABLED
-#endif
-
-
-/* CP microcode (from ATI) */
-static u32 radeon_cp_microcode[][2] = {
-	{ 0x21007000, 0000000000 },
-	{ 0x20007000, 0000000000 },
-	{ 0x000000b4, 0x00000004 },
-	{ 0x000000b8, 0x00000004 },
-	{ 0x6f5b4d4c, 0000000000 },
-	{ 0x4c4c427f, 0000000000 },
-	{ 0x5b568a92, 0000000000 },
-	{ 0x4ca09c6d, 0000000000 },
-	{ 0xad4c4c4c, 0000000000 },
-	{ 0x4ce1af3d, 0000000000 },
-	{ 0xd8afafaf, 0000000000 },
-	{ 0xd64c4cdc, 0000000000 },
-	{ 0x4cd10d10, 0000000000 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f242d, 0000000000 },
-	{ 0x00000012, 0x00000004 },
-	{ 0x000f0000, 0x00000016 },
-	{ 0x362f282d, 0000000000 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x000f0001, 0x00000016 },
-	{ 0x333a3730, 0000000000 },
-	{ 0x000077ef, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000021, 0x0000001a },
-	{ 0x00004000, 0x0000001e },
-	{ 0x00000017, 0x00000004 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000002 },
-	{ 0x00000017, 0x00000004 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x000037e1, 0x00000002 },
-	{ 0x040067e1, 0x00000006 },
-	{ 0x000077e0, 0x00000002 },
-	{ 0x000077e1, 0x00000002 },
-	{ 0x000077e1, 0x00000006 },
-	{ 0xffffffff, 0000000000 },
-	{ 0x10000000, 0000000000 },
-	{ 0x0003802b, 0x00000002 },
-	{ 0x040067e0, 0x00000006 },
-	{ 0x00007675, 0x00000002 },
-	{ 0x00007676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0003802c, 0x00000002 },
-	{ 0x04002676, 0x00000002 },
-	{ 0x00007677, 0x00000002 },
-	{ 0x00007678, 0x00000006 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0x0000002f, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x00000030, 0x00000018 },
-	{ 0x00000030, 0x00000018 },
-	{ 0000000000, 0x00000006 },
-	{ 0x01605000, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00098000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x64c0603e, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00080000, 0x00000016 },
-	{ 0000000000, 0000000000 },
-	{ 0x0400251d, 0x00000002 },
-	{ 0x00007580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x04002580, 0x00000002 },
-	{ 0x00067581, 0x00000002 },
-	{ 0x00000049, 0x00000004 },
-	{ 0x00005000, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x00019000, 0x00000002 },
-	{ 0x00011055, 0x00000014 },
-	{ 0x00000055, 0x00000012 },
-	{ 0x0400250f, 0x00000002 },
-	{ 0x0000504f, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007565, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x00000058, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x01e655b4, 0x00000002 },
-	{ 0x4401b0e4, 0x00000002 },
-	{ 0x01c110e4, 0x00000002 },
-	{ 0x26667066, 0x00000018 },
-	{ 0x040c2565, 0x00000002 },
-	{ 0x00000066, 0x00000018 },
-	{ 0x04002564, 0x00000002 },
-	{ 0x00007566, 0x00000002 },
-	{ 0x0000005d, 0x00000004 },
-	{ 0x00401069, 0x00000008 },
-	{ 0x00101000, 0x00000002 },
-	{ 0x000d80ff, 0x00000002 },
-	{ 0x0080006c, 0x00000008 },
-	{ 0x000f9000, 0x00000002 },
-	{ 0x000e00ff, 0x00000002 },
-	{ 0000000000, 0x00000006 },
-	{ 0x0000008f, 0x00000018 },
-	{ 0x0000005b, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00065000, 0x00000002 },
-	{ 0x00009000, 0x00000002 },
-	{ 0x00041000, 0x00000002 },
-	{ 0x0c00350e, 0x00000002 },
-	{ 0x00049000, 0x00000002 },
-	{ 0x00051000, 0x00000002 },
-	{ 0x01e785f8, 0x00000002 },
-	{ 0x00200000, 0x00000002 },
-	{ 0x0060007e, 0x0000000c },
-	{ 0x00007563, 0x00000002 },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x20007073, 0x00000004 },
-	{ 0x00005073, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00007576, 0x00000002 },
-	{ 0x00007577, 0x00000002 },
-	{ 0x0000750e, 0x00000002 },
-	{ 0x0000750f, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00600083, 0x0000000c },
-	{ 0x006075f0, 0x00000021 },
-	{ 0x000075f8, 0x00000002 },
-	{ 0x00000083, 0x00000004 },
-	{ 0x000a750e, 0x00000002 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x0020750f, 0x00000002 },
-	{ 0x00600086, 0x00000004 },
-	{ 0x00007570, 0x00000002 },
-	{ 0x00007571, 0x00000002 },
-	{ 0x00007572, 0x00000006 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00007568, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x00000095, 0x0000000c },
-	{ 0x00058000, 0x00000002 },
-	{ 0x0c607562, 0x00000002 },
-	{ 0x00000097, 0x00000004 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x00600096, 0x00000004 },
-	{ 0x400070e5, 0000000000 },
-	{ 0x000380e6, 0x00000002 },
-	{ 0x040025c5, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000a8, 0x0000001c },
-	{ 0x000650aa, 0x00000018 },
-	{ 0x040025bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x040075bc, 0000000000 },
-	{ 0x000075bb, 0x00000002 },
-	{ 0x000075bc, 0000000000 },
-	{ 0x00090000, 0x00000006 },
-	{ 0x00090000, 0x00000002 },
-	{ 0x000d8002, 0x00000006 },
-	{ 0x00007832, 0x00000002 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380e7, 0x00000002 },
-	{ 0x04002c97, 0x00000002 },
-	{ 0x00007820, 0x00000002 },
-	{ 0x00007821, 0x00000002 },
-	{ 0x00007800, 0000000000 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20077000, 0x00000002 },
-	{ 0x01200000, 0x00000002 },
-	{ 0x20007000, 0x00000002 },
-	{ 0x00061000, 0x00000002 },
-	{ 0x0120751b, 0x00000002 },
-	{ 0x8040750a, 0x00000002 },
-	{ 0x8040750b, 0x00000002 },
-	{ 0x00110000, 0x00000002 },
-	{ 0x000380e5, 0x00000002 },
-	{ 0x000000c6, 0x0000001c },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bd, 0x00000002 },
-	{ 0x000610aa, 0x00000018 },
-	{ 0x840075bb, 0x00000002 },
-	{ 0x000610ab, 0x00000018 },
-	{ 0x844075bc, 0x00000002 },
-	{ 0x000000c9, 0x00000004 },
-	{ 0x804075bd, 0x00000002 },
-	{ 0x800075bb, 0x00000002 },
-	{ 0x804075bc, 0x00000002 },
-	{ 0x00108000, 0x00000002 },
-	{ 0x01400000, 0x00000002 },
-	{ 0x006000cd, 0x0000000c },
-	{ 0x20c07000, 0x00000020 },
-	{ 0x000000cf, 0x00000012 },
-	{ 0x00800000, 0x00000006 },
-	{ 0x0080751d, 0x00000006 },
-	{ 0000000000, 0000000000 },
-	{ 0x0000775c, 0x00000002 },
-	{ 0x00a05000, 0x00000002 },
-	{ 0x00661000, 0x00000002 },
-	{ 0x0460275d, 0x00000020 },
-	{ 0x00004000, 0000000000 },
-	{ 0x01e00830, 0x00000002 },
-	{ 0x21007000, 0000000000 },
-	{ 0x6464614d, 0000000000 },
-	{ 0x69687420, 0000000000 },
-	{ 0x00000073, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00005000, 0x00000002 },
-	{ 0x000380d0, 0x00000002 },
-	{ 0x040025e0, 0x00000002 },
-	{ 0x000075e1, 0000000000 },
-	{ 0x00000001, 0000000000 },
-	{ 0x000380e0, 0x00000002 },
-	{ 0x04002394, 0x00000002 },
-	{ 0x00005000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0x00000008, 0000000000 },
-	{ 0x00000004, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-	{ 0000000000, 0000000000 },
-};
-
-
-int RADEON_READ_PLL(drm_device_t *dev, int addr)
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-
-	RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-	return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
-}
-
-#if RADEON_FIFO_DEBUG
-static void radeon_status( drm_radeon_private_t *dev_priv )
-{
-	printk( "%s:\n", __FUNCTION__ );
-	printk( "RBBM_STATUS = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
-	printk( "CP_RB_RTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
-	printk( "CP_RB_WTPR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
-	printk( "AIC_CNTL = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
-	printk( "AIC_STAT = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
-	printk( "AIC_PT_BASE = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
-	printk( "TLB_ADDR = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
-	printk( "TLB_DATA = 0x%08x\n",
-		(unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
-}
-#endif
-
-
-/* ================================================================
- * Engine, FIFO control
- */
-
-static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
-{
-	u32 tmp;
-	int i;
-
-	tmp  = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
-	tmp |= RADEON_RB2D_DC_FLUSH_ALL;
-	RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
-		       & RADEON_RB2D_DC_BUSY) ) {
-			return 0;
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
-				    int entries )
-{
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
-			      & RADEON_RBBM_FIFOCNT_MASK );
-		if ( slots >= entries ) return 0;
-		DRM_OS_DELAY( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
-{
-	int i, ret;
-
-	ret = radeon_do_wait_for_fifo( dev_priv, 64 );
-	if ( ret ) return ret;
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		if ( !(RADEON_READ( RADEON_RBBM_STATUS )
-		       & RADEON_RBBM_ACTIVE) ) {
-			radeon_do_pixcache_flush( dev_priv );
-			return 0;
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-#if RADEON_FIFO_DEBUG
-	DRM_ERROR( "failed!\n" );
-	radeon_status( dev_priv );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-
-/* ================================================================
- * CP control, initialization
- */
-
-/* Load the microcode for the CP */
-static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
-{
-	int i;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
-	for ( i = 0 ; i < 256 ; i++ ) {
-		RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
-			      radeon_cp_microcode[i][1] );
-		RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
-			      radeon_cp_microcode[i][0] );
-	}
-}
-
-/* Flush any pending commands to the CP.  This should only be used just
- * prior to a wait for idle, as it informs the engine that the command
- * stream is ending.
- */
-static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-#if 0
-	u32 tmp;
-
-	tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
-	RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
-#endif
-}
-
-/* Wait for the CP to go idle.
- */
-int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 6 );
-
-	RADEON_PURGE_CACHE();
-	RADEON_PURGE_ZCACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-
-	return radeon_do_wait_for_idle( dev_priv );
-}
-
-/* Start the Command Processor.
- */
-static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
-
-	dev_priv->cp_running = 1;
-
-	BEGIN_RING( 6 );
-
-	RADEON_PURGE_CACHE();
-	RADEON_PURGE_ZCACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-}
-
-/* Reset the Command Processor.  This will not flush any pending
- * commands, so you must wait for the CP command stream to complete
- * before calling this routine.
- */
-static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
-{
-	u32 cur_read_ptr;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	*dev_priv->ring.head = cur_read_ptr;
-	dev_priv->ring.tail = cur_read_ptr;
-}
-
-/* Stop the Command Processor.  This will not flush any pending
- * commands, so you must flush the command stream and wait for the CP
- * to go idle before calling this routine.
- */
-static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
-
-	dev_priv->cp_running = 0;
-}
-
-/* Reset the engine.  This will stop the CP if it is running.
- */
-static int radeon_do_engine_reset( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	radeon_do_pixcache_flush( dev_priv );
-
-	clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
-	mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
-					      RADEON_FORCEON_MCLKA |
-					      RADEON_FORCEON_MCLKB |
- 					      RADEON_FORCEON_YCLKA |
-					      RADEON_FORCEON_YCLKB |
-					      RADEON_FORCEON_MC |
-					      RADEON_FORCEON_AIC ) );
-
-	rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
-
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
-						RADEON_SOFT_RESET_CP |
-						RADEON_SOFT_RESET_HI |
-						RADEON_SOFT_RESET_SE |
-						RADEON_SOFT_RESET_RE |
-						RADEON_SOFT_RESET_PP |
-						RADEON_SOFT_RESET_E2 |
-						RADEON_SOFT_RESET_RB ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
-						~( RADEON_SOFT_RESET_CP |
-						   RADEON_SOFT_RESET_HI |
-						   RADEON_SOFT_RESET_SE |
-						   RADEON_SOFT_RESET_RE |
-						   RADEON_SOFT_RESET_PP |
-						   RADEON_SOFT_RESET_E2 |
-						   RADEON_SOFT_RESET_RB ) ) );
-	RADEON_READ( RADEON_RBBM_SOFT_RESET );
-
-
-	RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
-	RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
-	RADEON_WRITE( RADEON_RBBM_SOFT_RESET,  rbbm_soft_reset );
-
-	/* Reset the CP ring */
-	radeon_do_cp_reset( dev_priv );
-
-	/* The CP is no longer running after an engine reset */
-	dev_priv->cp_running = 0;
-
-	/* Reset any pending vertex, indirect buffers */
-	radeon_freelist_reset( dev );
-
-	return 0;
-}
-
-static void radeon_cp_init_ring_buffer( drm_device_t *dev,
-				        drm_radeon_private_t *dev_priv )
-{
-	u32 ring_start, cur_read_ptr;
-	u32 tmp;
-
-	/* Initialize the memory controller */
-	RADEON_WRITE( RADEON_MC_FB_LOCATION,
-		      (dev_priv->agp_vm_start - 1) & 0xffff0000 );
-
-	if ( !dev_priv->is_pci ) {
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION,
-			      (((dev_priv->agp_vm_start - 1 +
-				 dev_priv->agp_size) & 0xffff0000) |
-			       (dev_priv->agp_vm_start >> 16)) );
-	}
-
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		ring_start = (dev_priv->cp_ring->offset
-			      - dev->agp->base
-			      + dev_priv->agp_vm_start);
-       else
-#endif
-		ring_start = (dev_priv->cp_ring->offset
-			      - dev->sg->handle
-			      + dev_priv->agp_vm_start);
-
-	RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
-
-	/* Set the write pointer delay */
-	RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
-
-	/* Initialize the ring buffer's read and write pointers */
-	cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
-	RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
-	*dev_priv->ring.head = cur_read_ptr;
-	dev_priv->ring.tail = cur_read_ptr;
-
-#if __REALLY_HAVE_SG
-	if ( !dev_priv->is_pci ) {
-#endif
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			      dev_priv->ring_rptr->offset );
-#if __REALLY_HAVE_SG
-	} else {
-		drm_sg_mem_t *entry = dev->sg;
-		unsigned long tmp_ofs, page_ofs;
-
-		tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
-		page_ofs = tmp_ofs >> PAGE_SHIFT;
-
-		RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
-			     entry->busaddr[page_ofs]);
-		DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08x\n",
-			   entry->busaddr[page_ofs],
-			   entry->handle + tmp_ofs );
-	}
-#endif
-
-	/* Set ring buffer size */
-	RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
-
-	radeon_do_wait_for_idle( dev_priv );
-
-	/* Turn on bus mastering */
-	tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
-	RADEON_WRITE( RADEON_BUS_CNTL, tmp );
-
-	/* Sync everything up */
-	RADEON_WRITE( RADEON_ISYNC_CNTL,
-		      (RADEON_ISYNC_ANY2D_IDLE3D |
-		       RADEON_ISYNC_ANY3D_IDLE2D |
-		       RADEON_ISYNC_WAIT_IDLEGUI |
-		       RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
-}
-
-static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
-{
-	drm_radeon_private_t *dev_priv;
-	drm_map_list_entry_t *listentry;
-	u32 tmp;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
-	if ( dev_priv == NULL )
-		DRM_OS_RETURN( ENOMEM );
-
-	memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
-
-	dev_priv->is_pci = init->is_pci;
-
-#if !defined(PCIGART_ENABLED)
-	/* PCI support is not 100% working, so we disable it here.
-	 */
-	if ( dev_priv->is_pci ) {
-		DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN( EINVAL );
-	}
-#endif
-
-	if ( dev_priv->is_pci && !dev->sg ) {
-		DRM_ERROR( "PCI GART memory not allocated!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	dev_priv->usec_timeout = init->usec_timeout;
-	if ( dev_priv->usec_timeout < 1 ||
-	     dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
-		DRM_DEBUG( "TIMEOUT problem!\n" );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	dev_priv->cp_mode = init->cp_mode;
-
-	/* Simple idle check.
-	 */
-	atomic_set( &dev_priv->idle_count, 0 );
-
-	/* We don't support anything other than bus-mastering ring mode,
-	 * but the ring can be in either AGP or PCI space for the ring
-	 * read pointer.
-	 */
-	if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
-	     ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
-		DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	switch ( init->fb_bpp ) {
-	case 16:
-		dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
-		break;
-	case 32:
-	default:
-		dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
-		break;
-	}
-	dev_priv->front_offset	= init->front_offset;
-	dev_priv->front_pitch	= init->front_pitch;
-	dev_priv->back_offset	= init->back_offset;
-	dev_priv->back_pitch	= init->back_pitch;
-
-	switch ( init->depth_bpp ) {
-	case 16:
-		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
-		break;
-	case 32:
-	default:
-		dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
-		break;
-	}
-	dev_priv->depth_offset	= init->depth_offset;
-	dev_priv->depth_pitch	= init->depth_pitch;
-
-	dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
-					(dev_priv->front_offset >> 10));
-	dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
-				       (dev_priv->back_offset >> 10));
-	dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
-					(dev_priv->depth_offset >> 10));
-
-	/* Hardware state for depth clears.  Remove this if/when we no
-	 * longer clear the depth buffer with a 3D rectangle.  Hard-code
-	 * all values to prevent unwanted 3D state from slipping through
-	 * and screwing with the clear operation.
-	 */
-	dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
-					   (dev_priv->color_fmt << 10) |
-					   RADEON_ZBLOCK16);
-
-	dev_priv->depth_clear.rb3d_zstencilcntl = 
-		(dev_priv->depth_fmt |
-		 RADEON_Z_TEST_ALWAYS |
-		 RADEON_STENCIL_TEST_ALWAYS |
-		 RADEON_STENCIL_S_FAIL_REPLACE |
-		 RADEON_STENCIL_ZPASS_REPLACE |
-		 RADEON_STENCIL_ZFAIL_REPLACE |
-		 RADEON_Z_WRITE_ENABLE);
-
-	dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
-					 RADEON_BFACE_SOLID |
-					 RADEON_FFACE_SOLID |
-					 RADEON_FLAT_SHADE_VTX_LAST |
-					 RADEON_DIFFUSE_SHADE_FLAT |
-					 RADEON_ALPHA_SHADE_FLAT |
-					 RADEON_SPECULAR_SHADE_FLAT |
-					 RADEON_FOG_SHADE_FLAT |
-					 RADEON_VTX_PIX_CENTER_OGL |
-					 RADEON_ROUND_MODE_TRUNC |
-					 RADEON_ROUND_PREC_8TH_PIX);
-
-	TAILQ_FOREACH(listentry, dev->maplist, link) {
-		drm_map_t *map = listentry->map;
-		if (map->type == _DRM_SHM &&
-			map->flags & _DRM_CONTAINS_LOCK) {
-			dev_priv->sarea = map;
-			break;
-		}
-	}
-
-	if(!dev_priv->sarea) {
-		DRM_ERROR("could not find sarea!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
-	if(!dev_priv->fb) {
-		DRM_ERROR("could not find framebuffer!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
-	if(!dev_priv->mmio) {
-		DRM_ERROR("could not find mmio region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
-	if(!dev_priv->cp_ring) {
-		DRM_ERROR("could not find cp ring region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
-	if(!dev_priv->ring_rptr) {
-		DRM_ERROR("could not find ring read pointer!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-	DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
-	if(!dev_priv->buffers) {
-		DRM_ERROR("could not find dma buffer region!\n");
-		dev->dev_private = (void *)dev_priv;
-		radeon_do_cleanup_cp(dev);
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	if ( !dev_priv->is_pci ) {
-		DRM_FIND_MAP( dev_priv->agp_textures,
-			      init->agp_textures_offset );
-		if(!dev_priv->agp_textures) {
-			DRM_ERROR("could not find agp texture region!\n");
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			DRM_OS_RETURN(EINVAL);
-		}
-	}
-
-	dev_priv->sarea_priv =
-		(drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
-				       init->sarea_priv_offset);
-
-	if ( !dev_priv->is_pci ) {
-		DRM_IOREMAP( dev_priv->cp_ring );
-		DRM_IOREMAP( dev_priv->ring_rptr );
-		DRM_IOREMAP( dev_priv->buffers );
-		if(!dev_priv->cp_ring->handle ||
-		   !dev_priv->ring_rptr->handle ||
-		   !dev_priv->buffers->handle) {
-			DRM_ERROR("could not find ioremap agp regions!\n");
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			DRM_OS_RETURN(EINVAL);
-		}
-	} else {
-		dev_priv->cp_ring->handle =
-			(void *)dev_priv->cp_ring->offset;
-		dev_priv->ring_rptr->handle =
-			(void *)dev_priv->ring_rptr->offset;
-		dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
-
-		DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
-			   dev_priv->cp_ring->handle );
-		DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
-			   dev_priv->ring_rptr->handle );
-		DRM_DEBUG( "dev_priv->buffers->handle %p\n",
-			   dev_priv->buffers->handle );
-	}
-
-
-	dev_priv->agp_size = init->agp_size;
-	dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
-#if __REALLY_HAVE_AGP
-	if ( !dev_priv->is_pci )
-		dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
-						- dev->agp->base
-						+ dev_priv->agp_vm_start);
-	else
-#endif
-		dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
-						- dev->sg->handle
-						+ dev_priv->agp_vm_start);
-
-	DRM_DEBUG( "dev_priv->agp_size %d\n",
-		   dev_priv->agp_size );
-	DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
-		   dev_priv->agp_vm_start );
-	DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
-		   dev_priv->agp_buffers_offset );
-
-	dev_priv->ring.head = ((__volatile__ u32 *)
-			       dev_priv->ring_rptr->handle);
-
-	dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
-	dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
-			      + init->ring_size / sizeof(u32));
-	dev_priv->ring.size = init->ring_size;
-	dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
-
-	dev_priv->ring.tail_mask =
-		(dev_priv->ring.size / sizeof(u32)) - 1;
-
-	dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
-
-#if 0
-	/* Initialize the scratch register pointer.  This will cause
-	 * the scratch register values to be written out to memory
-	 * whenever they are updated.
-	 * FIXME: This doesn't quite work yet, so we're disabling it
-	 * for the release.
-	 */
-	RADEON_WRITE( RADEON_SCRATCH_ADDR, (dev_priv->ring_rptr->offset +
-					    RADEON_SCRATCH_REG_OFFSET) );
-	RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
-#endif
-
-	dev_priv->scratch = ((__volatile__ u32 *)
-			     dev_priv->ring_rptr->handle +
-			     (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
-
-	dev_priv->sarea_priv->last_frame = 0;
-	RADEON_WRITE( RADEON_LAST_FRAME_REG,
-		      dev_priv->sarea_priv->last_frame );
-
-	dev_priv->sarea_priv->last_dispatch = 0;
-	RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
-		      dev_priv->sarea_priv->last_dispatch );
-
-	dev_priv->sarea_priv->last_clear = 0;
-	RADEON_WRITE( RADEON_LAST_CLEAR_REG,
-		      dev_priv->sarea_priv->last_clear );
-
-#if __REALLY_HAVE_SG
-	if ( dev_priv->is_pci ) {
-		if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
-					    &dev_priv->bus_pci_gart)) {
-			DRM_ERROR( "failed to init PCI GART!\n" );
-			dev->dev_private = (void *)dev_priv;
-			radeon_do_cleanup_cp(dev);
-			DRM_OS_RETURN(ENOMEM);
-		}
-		/* Turn on PCI GART
-		 */
-		tmp = RADEON_READ( RADEON_AIC_CNTL )
-		      | RADEON_PCIGART_TRANSLATE_EN;
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-
-		/* set PCI GART page-table base address
-		 */
-		RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
-
-		/* set address range for PCI address translate
-		 */
-		RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
-		RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
-						  + dev_priv->agp_size - 1);
-
-		/* Turn off AGP aperture -- is this required for PCIGART?
-		 */
-		RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
-		RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
-	} else {
-#endif
-		/* Turn off PCI GART
-		 */
-		tmp = RADEON_READ( RADEON_AIC_CNTL )
-		      & ~RADEON_PCIGART_TRANSLATE_EN;
-		RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-#if __REALLY_HAVE_SG
-	}
-#endif
-
-	radeon_cp_load_microcode( dev_priv );
-	radeon_cp_init_ring_buffer( dev, dev_priv );
-
-#if ROTATE_BUFS
-	dev_priv->last_buf = 0;
-#endif
-
-	dev->dev_private = (void *)dev_priv;
-
-	radeon_do_engine_reset( dev );
-
-	return 0;
-}
-
-int radeon_do_cleanup_cp( drm_device_t *dev )
-{
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	if ( dev->dev_private ) {
-		drm_radeon_private_t *dev_priv = dev->dev_private;
-
-#if __REALLY_HAVE_SG
-		if ( !dev_priv->is_pci ) {
-#endif
-			DRM_IOREMAPFREE( dev_priv->cp_ring );
-			DRM_IOREMAPFREE( dev_priv->ring_rptr );
-			DRM_IOREMAPFREE( dev_priv->buffers );
-#if __REALLY_HAVE_SG
-		} else {
-			if (!DRM(ati_pcigart_cleanup)( dev,
-						dev_priv->phys_pci_gart,
-						dev_priv->bus_pci_gart ))
-				DRM_ERROR( "failed to cleanup PCI GART!\n" );
-		}
-#endif
-
-		DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
-			   DRM_MEM_DRIVER );
-		dev->dev_private = NULL;
-	}
-
-	return 0;
-}
-
-int radeon_cp_init( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_init_t init;
-
-	DRM_OS_KRNFROMUSR( init, (drm_radeon_init_t *) data, sizeof(init) );
-
-	switch ( init.func ) {
-	case RADEON_INIT_CP:
-		return radeon_do_init_cp( dev, &init );
-	case RADEON_CLEANUP_CP:
-		return radeon_do_cleanup_cp( dev );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-int radeon_cp_start( DRM_OS_IOCTL )
-{
- 	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( dev_priv->cp_running ) {
-		DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
-		return 0;
-	}
-	if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
-		DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
-			   __FUNCTION__, dev_priv->cp_mode );
-		return 0;
-	}
-
-	radeon_do_cp_start( dev_priv );
-
-	return 0;
-}
-
-/* Stop the CP.  The engine must have been idled before calling this
- * routine.
- */
-int radeon_cp_stop( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_cp_stop_t stop;
-	int ret;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( stop, (drm_radeon_cp_stop_t *) data, sizeof(stop) );
-
-	/* Flush any pending CP commands.  This ensures any outstanding
-	 * commands are exectuted by the engine before we turn it off.
-	 */
-	if ( stop.flush ) {
-		radeon_do_cp_flush( dev_priv );
-	}
-
-	/* If we fail to make the engine go idle, we return an error
-	 * code so that the DRM ioctl wrapper can try again.
-	 */
-	if ( stop.idle ) {
-		ret = radeon_do_cp_idle( dev_priv );
-		if ( ret ) return ret;
-	}
-
-	/* Finally, we can turn off the CP.  If the engine isn't idle,
-	 * we will get some dropped triangles as they won't be fully
-	 * rendered before the CP is shut down.
-	 */
-	radeon_do_cp_stop( dev_priv );
-
-	/* Reset the engine */
-	radeon_do_engine_reset( dev );
-
-	return 0;
-}
-
-/* Just reset the CP ring.  Called as part of an X Server engine reset.
- */
-int radeon_cp_reset( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	radeon_do_cp_reset( dev_priv );
-
-	/* The CP is no longer running after an engine reset */
-	dev_priv->cp_running = 0;
-
-	return 0;
-}
-
-int radeon_cp_idle( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return radeon_do_cp_idle( dev_priv );
-}
-
-int radeon_engine_reset( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	return radeon_do_engine_reset( dev );
-}
-
-
-/* ================================================================
- * Fullscreen mode
- */
-
-static int radeon_do_init_pageflip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	dev_priv->crtc_offset =      RADEON_READ( RADEON_CRTC_OFFSET );
-	dev_priv->crtc_offset_cntl = RADEON_READ( RADEON_CRTC_OFFSET_CNTL );
-
-	RADEON_WRITE( RADEON_CRTC_OFFSET, dev_priv->front_offset );
-	RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL,
-		      dev_priv->crtc_offset_cntl |
-		      RADEON_CRTC_OFFSET_FLIP_CNTL );
-
-	dev_priv->page_flipping = 1;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int radeon_do_cleanup_pageflip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	RADEON_WRITE( RADEON_CRTC_OFFSET,      dev_priv->crtc_offset );
-	RADEON_WRITE( RADEON_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
-
-	dev_priv->page_flipping = 0;
-	dev_priv->current_page = 0;
-
-	return 0;
-}
-
-int radeon_fullscreen( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_fullscreen_t fs;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( fs, (drm_radeon_fullscreen_t *) data,
-			     sizeof(fs) );
-
-	switch ( fs.func ) {
-	case RADEON_INIT_FULLSCREEN:
-		return radeon_do_init_pageflip( dev );
-	case RADEON_CLEANUP_FULLSCREEN:
-		return radeon_do_cleanup_pageflip( dev );
-	}
-
-	DRM_OS_RETURN( EINVAL );
-}
-
-
-/* ================================================================
- * Freelist management
- */
-#define RADEON_BUFFER_USED	0xffffffff
-#define RADEON_BUFFER_FREE	0
-
-#if 0
-static int radeon_freelist_init( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_radeon_freelist_t *entry;
-	int i;
-
-	dev_priv->head = DRM(alloc)( sizeof(drm_radeon_freelist_t),
-				     DRM_MEM_DRIVER );
-	if ( dev_priv->head == NULL )
-		DRM_OS_RETURN( ENOMEM );
-
-	memset( dev_priv->head, 0, sizeof(drm_radeon_freelist_t) );
-	dev_priv->head->age = RADEON_BUFFER_USED;
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-
-		entry = DRM(alloc)( sizeof(drm_radeon_freelist_t),
-				    DRM_MEM_DRIVER );
-		if ( !entry ) DRM_OS_RETURN( ENOMEM );
-
-		entry->age = RADEON_BUFFER_FREE;
-		entry->buf = buf;
-		entry->prev = dev_priv->head;
-		entry->next = dev_priv->head->next;
-		if ( !entry->next )
-			dev_priv->tail = entry;
-
-		buf_priv->discard = 0;
-		buf_priv->dispatched = 0;
-		buf_priv->list_entry = entry;
-
-		dev_priv->head->next = entry;
-
-		if ( dev_priv->head->next )
-			dev_priv->head->next->prev = entry;
-	}
-
-	return 0;
-
-}
-#endif
-
-drm_buf_t *radeon_freelist_get( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_buf_t *buf;
-	int i, t;
-#if ROTATE_BUFS
-	int start;
-#endif
-
-	/* FIXME: Optimize -- use freelist code */
-
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		buf = dma->buflist[i];
-		buf_priv = buf->dev_private;
-		if ( buf->pid == 0 ) {
-			DRM_DEBUG( "  ret buf=%d last=%d pid=0\n",
-				   buf->idx, dev_priv->last_buf );
-			return buf;
-		}
-		DRM_DEBUG( "    skipping buf=%d pid=%d\n",
-			   buf->idx, buf->pid );
-	}
-
-#if ROTATE_BUFS
-	if ( ++dev_priv->last_buf >= dma->buf_count )
-		dev_priv->last_buf = 0;
-	start = dev_priv->last_buf;
-#endif
-	for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
-#if 0
-		/* FIXME: Disable this for now */
-		u32 done_age = dev_priv->scratch[RADEON_LAST_DISPATCH];
-#else
-		u32 done_age = RADEON_READ( RADEON_LAST_DISPATCH_REG );
-#endif
-#if ROTATE_BUFS
-		for ( i = start ; i < dma->buf_count ; i++ ) {
-#else
-		for ( i = 0 ; i < dma->buf_count ; i++ ) {
-#endif
-			buf = dma->buflist[i];
-			buf_priv = buf->dev_private;
-			if ( buf->pending && buf_priv->age <= done_age ) {
-				/* The buffer has been processed, so it
-				 * can now be used.
-				 */
-				buf->pending = 0;
-				DRM_DEBUG( "  ret buf=%d last=%d age=%d done=%d\n", buf->idx, dev_priv->last_buf, buf_priv->age, done_age );
-				return buf;
-			}
-			DRM_DEBUG( "    skipping buf=%d age=%d done=%d\n",
-				   buf->idx, buf_priv->age,
-				   done_age );
-#if ROTATE_BUFS
-			start = 0;
-#endif
-		}
-		DRM_OS_DELAY( 1 );
-	}
-
-	DRM_ERROR( "returning NULL!\n" );
-	return NULL;
-}
-
-void radeon_freelist_reset( drm_device_t *dev )
-{
-	drm_device_dma_t *dma = dev->dma;
-#if ROTATE_BUFS
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-#endif
-	int i;
-
-#if ROTATE_BUFS
-	dev_priv->last_buf = 0;
-#endif
-	for ( i = 0 ; i < dma->buf_count ; i++ ) {
-		drm_buf_t *buf = dma->buflist[i];
-		drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-		buf_priv->age = 0;
-	}
-}
-
-
-/* ================================================================
- * CP command submission
- */
-
-int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
-{
-	drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
-	int i;
-
-	for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
-		radeon_update_ring_snapshot( ring );
-		if ( ring->space > n )
-			return 0;
-		DRM_OS_DELAY( 1 );
-	}
-
-	/* FIXME: This return value is ignored in the BEGIN_RING macro! */
-#if RADEON_FIFO_DEBUG
-	radeon_status( dev_priv );
-	DRM_ERROR( "failed!\n" );
-#endif
-	DRM_OS_RETURN( EBUSY );
-}
-
-static int radeon_cp_get_buffers( drm_device_t *dev, drm_dma_t *d )
-{
-	int i;
-	drm_buf_t *buf;
-
-	for ( i = d->granted_count ; i < d->request_count ; i++ ) {
-		buf = radeon_freelist_get( dev );
-		if ( !buf ) DRM_OS_RETURN( EAGAIN );
-
-		buf->pid = DRM_OS_CURRENTPID;
-
-		if (DRM_OS_COPYTOUSR( &d->request_indices[i], &buf->idx,
-				   sizeof(buf->idx) ) )
-			DRM_OS_RETURN( EFAULT );
-		if (DRM_OS_COPYTOUSR( &d->request_sizes[i], &buf->total,
-				   sizeof(buf->total) ) )
-			DRM_OS_RETURN( EFAULT );
-
-		d->granted_count++;
-	}
-	return 0;
-}
-
-int radeon_cp_buffers( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_device_dma_t *dma = dev->dma;
-	int ret = 0;
-	drm_dma_t d;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) );
-
-	/* Please don't send us buffers.
-	 */
-	if ( d.send_count != 0 ) {
-		DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
-			   DRM_OS_CURRENTPID, d.send_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	/* We'll send you buffers.
-	 */
-	if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
-		DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
-			   DRM_OS_CURRENTPID, d.request_count, dma->buf_count );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	d.granted_count = 0;
-
-	if ( d.request_count ) {
-		ret = radeon_cp_get_buffers( dev, &d );
-	}
-
-	DRM_OS_KRNTOUSR( (drm_dma_t *) data, d, sizeof(d) );
-
-	return ret;
-}
diff --git a/bsd/radeon/radeon_drv.c b/bsd/radeon/radeon_drv.c
deleted file mode 100644
index 009f90c1..00000000
--- a/bsd/radeon/radeon_drv.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/* radeon_drv.c -- ATI Radeon driver -*- linux-c -*-
- * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
- *
- * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-
-
-#include <sys/types.h>
-#include <sys/bus.h>
-#include <pci/pcivar.h>
-#include <opt_drm_linux.h>
-
-#include "radeon.h"
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-#if __REALLY_HAVE_SG
-#include "ati_pcigart.h"
-#endif
-
-#define DRIVER_AUTHOR		"Gareth Hughes, VA Linux Systems Inc."
-
-#define DRIVER_NAME		"radeon"
-#define DRIVER_DESC		"ATI Radeon"
-#define DRIVER_DATE		"20010405"
-
-#define DRIVER_MAJOR		1
-#define DRIVER_MINOR		2
-#define DRIVER_PATCHLEVEL	0
-  
-/* Interface history:
- *
- * 1.1 - ??
- * 1.2 - Add vertex2 ioctl (keith)
- *     - Add stencil capability to clear ioctl (gareth, keith)
- *     - Increase MAX_TEXTURE_LEVELS (brian)
- */
-
-/* List acquired from http://www.yourvote.com/pci/pcihdr.h and xc/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
- * Please report to anholt@teleport.com inaccuracies or if a chip you have works that is marked unsupported here.
- */
-drm_chipinfo_t DRM(devicelist)[] = {
-	{0x1002, 0x5144, 1, "ATI Radeon QD"},
-	{0x1002, 0x5145, 1, "ATI Radeon QE"},
-	{0x1002, 0x5146, 1, "ATI Radeon QF"},
-	{0x1002, 0x5147, 1, "ATI Radeon QG"},
-	{0x1002, 0x5159, 1, "ATI Radeon VE"},
-	{0, 0, 0, NULL}
-};
-
-#define DRIVER_IOCTLS							     \
- [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_INIT)]    = { radeon_cp_init,     1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_START)]   = { radeon_cp_start,    1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_STOP)]    = { radeon_cp_stop,     1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_RESET)]   = { radeon_cp_reset,    1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CP_IDLE)]    = { radeon_cp_idle,     1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)]    = { radeon_engine_reset,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)]       = { radeon_cp_swap,     1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_CLEAR)]      = { radeon_cp_clear,    1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX)]     = { radeon_cp_vertex,   1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDICES)]    = { radeon_cp_indices,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_TEXTURE)]    = { radeon_cp_texture,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_STIPPLE)]    = { radeon_cp_stipple,  1, 0 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_INDIRECT)]   = { radeon_cp_indirect, 1, 1 }, \
- [DRM_IOCTL_NR(DRM_IOCTL_RADEON_VERTEX2)]    = { radeon_cp_vertex2,  1, 0 },
-
-
-#if 0
-/* GH: Count data sent to card via ring or vertex/indirect buffers.
- */
-#define __HAVE_COUNTERS         3
-#define __HAVE_COUNTER6         _DRM_STAT_IRQ
-#define __HAVE_COUNTER7         _DRM_STAT_PRIMARY
-#define __HAVE_COUNTER8         _DRM_STAT_SECONDARY
-#endif
-
-
-#include "drm_agpsupport.h"
-#include "drm_auth.h"
-#include "drm_bufs.h"
-#include "drm_context.h"
-#include "drm_dma.h"
-#include "drm_drawable.h"
-#include "drm_drv.h"
-
-
-#include "drm_fops.h"
-#include "drm_init.h"
-#include "drm_ioctl.h"
-#include "drm_lock.h"
-#include "drm_memory.h"
-#include "drm_vm.h"
-#include "drm_sysctl.h"
-#if __REALLY_HAVE_SG
-#include "drm_scatter.h"
-#endif
-
-DRIVER_MODULE(radeon, pci, radeon_driver, radeon_devclass, 0, 0);
diff --git a/bsd/radeon/radeon_drv.h b/bsd/radeon/radeon_drv.h
deleted file mode 100644
index cda5ef7d..00000000
--- a/bsd/radeon/radeon_drv.h
+++ /dev/null
@@ -1,733 +0,0 @@
-/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
- *
- * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All rights reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Kevin E. Martin <martin@valinux.com>
- *    Gareth Hughes <gareth@valinux.com>
- */
-
-#ifndef __RADEON_DRV_H__
-#define __RADEON_DRV_H__
-
-typedef struct drm_radeon_freelist {
-   	unsigned int age;
-   	drm_buf_t *buf;
-   	struct drm_radeon_freelist *next;
-   	struct drm_radeon_freelist *prev;
-} drm_radeon_freelist_t;
-
-typedef struct drm_radeon_ring_buffer {
-	u32 *start;
-	u32 *end;
-	int size;
-	int size_l2qw;
-
-	volatile u32 *head;
-	u32 tail;
-	u32 tail_mask;
-	int space;
-
-	int high_mark;
-} drm_radeon_ring_buffer_t;
-
-typedef struct drm_radeon_depth_clear_t {
-	u32 rb3d_cntl;
-	u32 rb3d_zstencilcntl;
-	u32 se_cntl;
-} drm_radeon_depth_clear_t;
-
-typedef struct drm_radeon_private {
-	drm_radeon_ring_buffer_t ring;
-	drm_radeon_sarea_t *sarea_priv;
-
-	int agp_size;
-	u32 agp_vm_start;
-	unsigned long agp_buffers_offset;
-
-	int cp_mode;
-	int cp_running;
-
-   	drm_radeon_freelist_t *head;
-   	drm_radeon_freelist_t *tail;
-/* FIXME: ROTATE_BUFS is a hask to cycle through bufs until freelist
-   code is used.  Note this hides a problem with the scratch register
-   (used to keep track of last buffer completed) being written to before
-   the last buffer has actually completed rendering. */
-#define ROTATE_BUFS 1
-#if ROTATE_BUFS
-	int last_buf;
-#endif
-	volatile u32 *scratch;
-
-	int usec_timeout;
-	int is_pci;
-	unsigned long phys_pci_gart;
-#if __REALLY_HAVE_SG
-	dma_addr_t bus_pci_gart;
-#endif
-
-	atomic_t idle_count;
-
-	int page_flipping;
-	int current_page;
-	u32 crtc_offset;
-	u32 crtc_offset_cntl;
-
-	u32 color_fmt;
-	unsigned int front_offset;
-	unsigned int front_pitch;
-	unsigned int back_offset;
-	unsigned int back_pitch;
-
-	u32 depth_fmt;
-	unsigned int depth_offset;
-	unsigned int depth_pitch;
-
-	u32 front_pitch_offset;
-	u32 back_pitch_offset;
-	u32 depth_pitch_offset;
-
-	drm_radeon_depth_clear_t depth_clear;
-
-	drm_map_t *sarea;
-	drm_map_t *fb;
-	drm_map_t *mmio;
-	drm_map_t *cp_ring;
-	drm_map_t *ring_rptr;
-	drm_map_t *buffers;
-	drm_map_t *agp_textures;
-} drm_radeon_private_t;
-
-typedef struct drm_radeon_buf_priv {
-	u32 age;
-	int prim;
-	int discard;
-	int dispatched;
-   	drm_radeon_freelist_t *list_entry;
-} drm_radeon_buf_priv_t;
-
-				/* radeon_cp.c */
-extern int radeon_cp_init( DRM_OS_IOCTL );
-extern int radeon_cp_start( DRM_OS_IOCTL );
-extern int radeon_cp_stop( DRM_OS_IOCTL );
-extern int radeon_cp_reset( DRM_OS_IOCTL );
-extern int radeon_cp_idle( DRM_OS_IOCTL );
-extern int radeon_engine_reset( DRM_OS_IOCTL );
-extern int radeon_fullscreen( DRM_OS_IOCTL );
-extern int radeon_cp_buffers( DRM_OS_IOCTL );
-
-extern void radeon_freelist_reset( drm_device_t *dev );
-extern drm_buf_t *radeon_freelist_get( drm_device_t *dev );
-
-extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n );
-
-static __inline__ void
-radeon_update_ring_snapshot( drm_radeon_ring_buffer_t *ring )
-{
-	ring->space = (*(volatile int *)ring->head - ring->tail) * sizeof(u32);
-	if ( ring->space <= 0 )
-		ring->space += ring->size;
-}
-
-extern int radeon_do_cp_idle( drm_radeon_private_t *dev_priv );
-extern int radeon_do_cleanup_cp( drm_device_t *dev );
-extern int radeon_do_cleanup_pageflip( drm_device_t *dev );
-
-				/* radeon_state.c */
-extern int radeon_cp_clear( DRM_OS_IOCTL );
-extern int radeon_cp_swap( DRM_OS_IOCTL );
-extern int radeon_cp_vertex( DRM_OS_IOCTL );
-extern int radeon_cp_indices( DRM_OS_IOCTL );
-extern int radeon_cp_texture( DRM_OS_IOCTL );
-extern int radeon_cp_stipple( DRM_OS_IOCTL );
-extern int radeon_cp_indirect( DRM_OS_IOCTL );
-extern int radeon_cp_vertex2( DRM_OS_IOCTL );
-
-/* Register definitions, register access macros and drmAddMap constants
- * for Radeon kernel driver.
- */
-
-#define RADEON_AGP_COMMAND		0x0f60
-#define RADEON_AUX_SCISSOR_CNTL		0x26f0
-#	define RADEON_EXCLUSIVE_SCISSOR_0	(1 << 24)
-#	define RADEON_EXCLUSIVE_SCISSOR_1	(1 << 25)
-#	define RADEON_EXCLUSIVE_SCISSOR_2	(1 << 26)
-#	define RADEON_SCISSOR_0_ENABLE		(1 << 28)
-#	define RADEON_SCISSOR_1_ENABLE		(1 << 29)
-#	define RADEON_SCISSOR_2_ENABLE		(1 << 30)
-
-#define RADEON_BUS_CNTL			0x0030
-#	define RADEON_BUS_MASTER_DIS		(1 << 6)
-
-#define RADEON_CLOCK_CNTL_DATA		0x000c
-#	define RADEON_PLL_WR_EN			(1 << 7)
-#define RADEON_CLOCK_CNTL_INDEX		0x0008
-#define RADEON_CONFIG_APER_SIZE		0x0108
-#define RADEON_CRTC_OFFSET		0x0224
-#define RADEON_CRTC_OFFSET_CNTL		0x0228
-#	define RADEON_CRTC_TILE_EN		(1 << 15)
-#	define RADEON_CRTC_OFFSET_FLIP_CNTL	(1 << 16)
-
-#define RADEON_RB3D_COLORPITCH		0x1c48
-#define RADEON_RB3D_DEPTHCLEARVALUE	0x1c30
-#define RADEON_RB3D_DEPTHXY_OFFSET	0x1c60
-
-#define RADEON_DP_GUI_MASTER_CNTL	0x146c
-#	define RADEON_GMC_SRC_PITCH_OFFSET_CNTL	(1 << 0)
-#	define RADEON_GMC_DST_PITCH_OFFSET_CNTL	(1 << 1)
-#	define RADEON_GMC_BRUSH_SOLID_COLOR	(13 << 4)
-#	define RADEON_GMC_BRUSH_NONE		(15 << 4)
-#	define RADEON_GMC_DST_16BPP		(4 << 8)
-#	define RADEON_GMC_DST_24BPP		(5 << 8)
-#	define RADEON_GMC_DST_32BPP		(6 << 8)
-#	define RADEON_GMC_DST_DATATYPE_SHIFT	8
-#	define RADEON_GMC_SRC_DATATYPE_COLOR	(3 << 12)
-#	define RADEON_DP_SRC_SOURCE_MEMORY	(2 << 24)
-#	define RADEON_DP_SRC_SOURCE_HOST_DATA	(3 << 24)
-#	define RADEON_GMC_CLR_CMP_CNTL_DIS	(1 << 28)
-#	define RADEON_GMC_WR_MSK_DIS		(1 << 30)
-#	define RADEON_ROP3_S			0x00cc0000
-#	define RADEON_ROP3_P			0x00f00000
-#define RADEON_DP_WRITE_MASK		0x16cc
-#define RADEON_DST_PITCH_OFFSET		0x142c
-#define RADEON_DST_PITCH_OFFSET_C	0x1c80
-#	define RADEON_DST_TILE_LINEAR		(0 << 30)
-#	define RADEON_DST_TILE_MACRO		(1 << 30)
-#	define RADEON_DST_TILE_MICRO		(2 << 30)
-#	define RADEON_DST_TILE_BOTH		(3 << 30)
-
-#define RADEON_SCRATCH_REG0		0x15e0
-#define RADEON_SCRATCH_REG1		0x15e4
-#define RADEON_SCRATCH_REG2		0x15e8
-#define RADEON_SCRATCH_REG3		0x15ec
-#define RADEON_SCRATCH_REG4		0x15f0
-#define RADEON_SCRATCH_REG5		0x15f4
-#define RADEON_SCRATCH_UMSK		0x0770
-#define RADEON_SCRATCH_ADDR		0x0774
-
-#define RADEON_HOST_PATH_CNTL		0x0130
-#	define RADEON_HDP_SOFT_RESET		(1 << 26)
-#	define RADEON_HDP_WC_TIMEOUT_MASK	(7 << 28)
-#	define RADEON_HDP_WC_TIMEOUT_28BCLK	(7 << 28)
-
-#define RADEON_ISYNC_CNTL		0x1724
-#	define RADEON_ISYNC_ANY2D_IDLE3D	(1 << 0)
-#	define RADEON_ISYNC_ANY3D_IDLE2D	(1 << 1)
-#	define RADEON_ISYNC_TRIG2D_IDLE3D	(1 << 2)
-#	define RADEON_ISYNC_TRIG3D_IDLE2D	(1 << 3)
-#	define RADEON_ISYNC_WAIT_IDLEGUI	(1 << 4)
-#	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
-
-#define RADEON_MC_AGP_LOCATION		0x014c
-#define RADEON_MC_FB_LOCATION		0x0148
-#define RADEON_MCLK_CNTL		0x0012
-#	define RADEON_FORCEON_MCLKA		(1 << 16)
-#	define RADEON_FORCEON_MCLKB		(1 << 17)
-#	define RADEON_FORCEON_YCLKA		(1 << 18)
-#	define RADEON_FORCEON_YCLKB		(1 << 19)
-#	define RADEON_FORCEON_MC		(1 << 20)
-#	define RADEON_FORCEON_AIC		(1 << 21)
-
-#define RADEON_PP_BORDER_COLOR_0	0x1d40
-#define RADEON_PP_BORDER_COLOR_1	0x1d44
-#define RADEON_PP_BORDER_COLOR_2	0x1d48
-#define RADEON_PP_CNTL			0x1c38
-#	define RADEON_SCISSOR_ENABLE		(1 <<  1)
-#define RADEON_PP_LUM_MATRIX		0x1d00
-#define RADEON_PP_MISC			0x1c14
-#define RADEON_PP_ROT_MATRIX_0		0x1d58
-#define RADEON_PP_TXFILTER_0		0x1c54
-#define RADEON_PP_TXFILTER_1		0x1c6c
-#define RADEON_PP_TXFILTER_2		0x1c84
-
-#define RADEON_RB2D_DSTCACHE_CTLSTAT	0x342c
-#	define RADEON_RB2D_DC_FLUSH		(3 << 0)
-#	define RADEON_RB2D_DC_FREE		(3 << 2)
-#	define RADEON_RB2D_DC_FLUSH_ALL		0xf
-#	define RADEON_RB2D_DC_BUSY		(1 << 31)
-#define RADEON_RB3D_CNTL		0x1c3c
-#	define RADEON_ALPHA_BLEND_ENABLE	(1 << 0)
-#	define RADEON_PLANE_MASK_ENABLE		(1 << 1)
-#	define RADEON_DITHER_ENABLE		(1 << 2)
-#	define RADEON_ROUND_ENABLE		(1 << 3)
-#	define RADEON_SCALE_DITHER_ENABLE	(1 << 4)
-#	define RADEON_DITHER_INIT		(1 << 5)
-#	define RADEON_ROP_ENABLE		(1 << 6)
-#	define RADEON_STENCIL_ENABLE		(1 << 7)
-#	define RADEON_Z_ENABLE			(1 << 8)
-#	define RADEON_DEPTH_XZ_OFFEST_ENABLE	(1 << 9)
-#	define RADEON_ZBLOCK8			(0 << 15)
-#	define RADEON_ZBLOCK16			(1 << 15)
-#define RADEON_RB3D_DEPTHOFFSET		0x1c24
-#define RADEON_RB3D_PLANEMASK		0x1d84
-#define RADEON_RB3D_STENCILREFMASK	0x1d7c
-#define RADEON_RB3D_ZCACHE_MODE		0x3250
-#define RADEON_RB3D_ZCACHE_CTLSTAT	0x3254
-#	define RADEON_RB3D_ZC_FLUSH		(1 << 0)
-#	define RADEON_RB3D_ZC_FREE		(1 << 2)
-#	define RADEON_RB3D_ZC_FLUSH_ALL		0x5
-#	define RADEON_RB3D_ZC_BUSY		(1 << 31)
-#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
-#	define RADEON_Z_TEST_MASK		(7 << 4)
-#	define RADEON_Z_TEST_ALWAYS		(7 << 4)
-#	define RADEON_STENCIL_TEST_ALWAYS	(7 << 12)
-#	define RADEON_STENCIL_S_FAIL_REPLACE	(2 << 16)
-#	define RADEON_STENCIL_ZPASS_REPLACE	(2 << 20)
-#	define RADEON_STENCIL_ZFAIL_REPLACE	(2 << 24)
-#	define RADEON_Z_WRITE_ENABLE		(1 << 30)
-#define RADEON_RBBM_SOFT_RESET		0x00f0
-#	define RADEON_SOFT_RESET_CP		(1 <<  0)
-#	define RADEON_SOFT_RESET_HI		(1 <<  1)
-#	define RADEON_SOFT_RESET_SE		(1 <<  2)
-#	define RADEON_SOFT_RESET_RE		(1 <<  3)
-#	define RADEON_SOFT_RESET_PP		(1 <<  4)
-#	define RADEON_SOFT_RESET_E2		(1 <<  5)
-#	define RADEON_SOFT_RESET_RB		(1 <<  6)
-#	define RADEON_SOFT_RESET_HDP		(1 <<  7)
-#define RADEON_RBBM_STATUS		0x0e40
-#	define RADEON_RBBM_FIFOCNT_MASK		0x007f
-#	define RADEON_RBBM_ACTIVE		(1 << 31)
-#define RADEON_RE_LINE_PATTERN		0x1cd0
-#define RADEON_RE_MISC			0x26c4
-#define RADEON_RE_TOP_LEFT		0x26c0
-#define RADEON_RE_WIDTH_HEIGHT		0x1c44
-#define RADEON_RE_STIPPLE_ADDR		0x1cc8
-#define RADEON_RE_STIPPLE_DATA		0x1ccc
-
-#define RADEON_SCISSOR_TL_0		0x1cd8
-#define RADEON_SCISSOR_BR_0		0x1cdc
-#define RADEON_SCISSOR_TL_1		0x1ce0
-#define RADEON_SCISSOR_BR_1		0x1ce4
-#define RADEON_SCISSOR_TL_2		0x1ce8
-#define RADEON_SCISSOR_BR_2		0x1cec
-#define RADEON_SE_COORD_FMT		0x1c50
-#define RADEON_SE_CNTL			0x1c4c
-#	define RADEON_FFACE_CULL_CW		(0 << 0)
-#	define RADEON_BFACE_SOLID		(3 << 1)
-#	define RADEON_FFACE_SOLID		(3 << 3)
-#	define RADEON_FLAT_SHADE_VTX_LAST	(3 << 6)
-#	define RADEON_DIFFUSE_SHADE_FLAT	(1 << 8)
-#	define RADEON_DIFFUSE_SHADE_GOURAUD	(2 << 8)
-#	define RADEON_ALPHA_SHADE_FLAT		(1 << 10)
-#	define RADEON_ALPHA_SHADE_GOURAUD	(2 << 10)
-#	define RADEON_SPECULAR_SHADE_FLAT	(1 << 12)
-#	define RADEON_SPECULAR_SHADE_GOURAUD	(2 << 12)
-#	define RADEON_FOG_SHADE_FLAT		(1 << 14)
-#	define RADEON_FOG_SHADE_GOURAUD		(2 << 14)
-#	define RADEON_VPORT_XY_XFORM_ENABLE	(1 << 24)
-#	define RADEON_VPORT_Z_XFORM_ENABLE	(1 << 25)
-#	define RADEON_VTX_PIX_CENTER_OGL	(1 << 27)
-#	define RADEON_ROUND_MODE_TRUNC		(0 << 28)
-#	define RADEON_ROUND_PREC_8TH_PIX	(1 << 30)
-#define RADEON_SE_CNTL_STATUS		0x2140
-#define RADEON_SE_LINE_WIDTH		0x1db8
-#define RADEON_SE_VPORT_XSCALE		0x1d98
-#define RADEON_SE_ZBIAS_FACTOR		0x1db0
-#define RADEON_SURFACE_ACCESS_FLAGS	0x0bf8
-#define RADEON_SURFACE_ACCESS_CLR	0x0bfc
-#define RADEON_SURFACE_CNTL		0x0b00
-#	define RADEON_SURF_TRANSLATION_DIS	(1 << 8)
-#	define RADEON_NONSURF_AP0_SWP_MASK	(3 << 20)
-#	define RADEON_NONSURF_AP0_SWP_LITTLE	(0 << 20)
-#	define RADEON_NONSURF_AP0_SWP_BIG16	(1 << 20)
-#	define RADEON_NONSURF_AP0_SWP_BIG32	(2 << 20)
-#	define RADEON_NONSURF_AP1_SWP_MASK	(3 << 22)
-#	define RADEON_NONSURF_AP1_SWP_LITTLE	(0 << 22)
-#	define RADEON_NONSURF_AP1_SWP_BIG16	(1 << 22)
-#	define RADEON_NONSURF_AP1_SWP_BIG32	(2 << 22)
-#define RADEON_SURFACE0_INFO		0x0b0c
-#	define RADEON_SURF_PITCHSEL_MASK	(0x1ff << 0)
-#	define RADEON_SURF_TILE_MODE_MASK	(3 << 16)
-#	define RADEON_SURF_TILE_MODE_MACRO	(0 << 16)
-#	define RADEON_SURF_TILE_MODE_MICRO	(1 << 16)
-#	define RADEON_SURF_TILE_MODE_32BIT_Z	(2 << 16)
-#	define RADEON_SURF_TILE_MODE_16BIT_Z	(3 << 16)
-#define RADEON_SURFACE0_LOWER_BOUND	0x0b04
-#define RADEON_SURFACE0_UPPER_BOUND	0x0b08
-#define RADEON_SURFACE1_INFO		0x0b1c
-#define RADEON_SURFACE1_LOWER_BOUND	0x0b14
-#define RADEON_SURFACE1_UPPER_BOUND	0x0b18
-#define RADEON_SURFACE2_INFO		0x0b2c
-#define RADEON_SURFACE2_LOWER_BOUND	0x0b24
-#define RADEON_SURFACE2_UPPER_BOUND	0x0b28
-#define RADEON_SURFACE3_INFO		0x0b3c
-#define RADEON_SURFACE3_LOWER_BOUND	0x0b34
-#define RADEON_SURFACE3_UPPER_BOUND	0x0b38
-#define RADEON_SURFACE4_INFO		0x0b4c
-#define RADEON_SURFACE4_LOWER_BOUND	0x0b44
-#define RADEON_SURFACE4_UPPER_BOUND	0x0b48
-#define RADEON_SURFACE5_INFO		0x0b5c
-#define RADEON_SURFACE5_LOWER_BOUND	0x0b54
-#define RADEON_SURFACE5_UPPER_BOUND	0x0b58
-#define RADEON_SURFACE6_INFO		0x0b6c
-#define RADEON_SURFACE6_LOWER_BOUND	0x0b64
-#define RADEON_SURFACE6_UPPER_BOUND	0x0b68
-#define RADEON_SURFACE7_INFO		0x0b7c
-#define RADEON_SURFACE7_LOWER_BOUND	0x0b74
-#define RADEON_SURFACE7_UPPER_BOUND	0x0b78
-#define RADEON_SW_SEMAPHORE		0x013c
-
-#define RADEON_WAIT_UNTIL		0x1720
-#	define RADEON_WAIT_CRTC_PFLIP		(1 << 0)
-#	define RADEON_WAIT_2D_IDLECLEAN		(1 << 16)
-#	define RADEON_WAIT_3D_IDLECLEAN		(1 << 17)
-#	define RADEON_WAIT_HOST_IDLECLEAN	(1 << 18)
-
-#define RADEON_RB3D_ZMASKOFFSET		0x1c34
-#define RADEON_RB3D_ZSTENCILCNTL	0x1c2c
-#	define RADEON_DEPTH_FORMAT_16BIT_INT_Z	(0 << 0)
-#	define RADEON_DEPTH_FORMAT_24BIT_INT_Z	(2 << 0)
-
-
-/* CP registers */
-#define RADEON_CP_ME_RAM_ADDR		0x07d4
-#define RADEON_CP_ME_RAM_RADDR		0x07d8
-#define RADEON_CP_ME_RAM_DATAH		0x07dc
-#define RADEON_CP_ME_RAM_DATAL		0x07e0
-
-#define RADEON_CP_RB_BASE		0x0700
-#define RADEON_CP_RB_CNTL		0x0704
-#define RADEON_CP_RB_RPTR_ADDR		0x070c
-#define RADEON_CP_RB_RPTR		0x0710
-#define RADEON_CP_RB_WPTR		0x0714
-
-#define RADEON_CP_RB_WPTR_DELAY		0x0718
-#	define RADEON_PRE_WRITE_TIMER_SHIFT	0
-#	define RADEON_PRE_WRITE_LIMIT_SHIFT	23
-
-#define RADEON_CP_IB_BASE		0x0738
-
-#define RADEON_CP_CSQ_CNTL		0x0740
-#	define RADEON_CSQ_CNT_PRIMARY_MASK	(0xff << 0)
-#	define RADEON_CSQ_PRIDIS_INDDIS		(0 << 28)
-#	define RADEON_CSQ_PRIPIO_INDDIS		(1 << 28)
-#	define RADEON_CSQ_PRIBM_INDDIS		(2 << 28)
-#	define RADEON_CSQ_PRIPIO_INDBM		(3 << 28)
-#	define RADEON_CSQ_PRIBM_INDBM		(4 << 28)
-#	define RADEON_CSQ_PRIPIO_INDPIO		(15 << 28)
-
-#define RADEON_AIC_CNTL			0x01d0
-#	define RADEON_PCIGART_TRANSLATE_EN	(1 << 0)
-#define RADEON_AIC_STAT			0x01d4
-#define RADEON_AIC_PT_BASE		0x01d8
-#define RADEON_AIC_LO_ADDR		0x01dc
-#define RADEON_AIC_HI_ADDR		0x01e0
-#define RADEON_AIC_TLB_ADDR		0x01e4
-#define RADEON_AIC_TLB_DATA		0x01e8
-
-/* CP command packets */
-#define RADEON_CP_PACKET0		0x00000000
-#	define RADEON_ONE_REG_WR		(1 << 15)
-#define RADEON_CP_PACKET1		0x40000000
-#define RADEON_CP_PACKET2		0x80000000
-#define RADEON_CP_PACKET3		0xC0000000
-#	define RADEON_3D_RNDR_GEN_INDX_PRIM	0x00002300
-#	define RADEON_WAIT_FOR_IDLE		0x00002600
-#	define RADEON_3D_DRAW_IMMD		0x00002900
-#	define RADEON_3D_CLEAR_ZMASK		0x00003200
-#	define RADEON_CNTL_HOSTDATA_BLT		0x00009400
-#	define RADEON_CNTL_PAINT_MULTI		0x00009A00
-#	define RADEON_CNTL_BITBLT_MULTI		0x00009B00
-
-#define RADEON_CP_PACKET_MASK		0xC0000000
-#define RADEON_CP_PACKET_COUNT_MASK	0x3fff0000
-#define RADEON_CP_PACKET0_REG_MASK	0x000007ff
-#define RADEON_CP_PACKET1_REG0_MASK	0x000007ff
-#define RADEON_CP_PACKET1_REG1_MASK	0x003ff800
-
-#define RADEON_VTX_Z_PRESENT			(1 << 31)
-
-#define RADEON_PRIM_TYPE_NONE			(0 << 0)
-#define RADEON_PRIM_TYPE_POINT			(1 << 0)
-#define RADEON_PRIM_TYPE_LINE			(2 << 0)
-#define RADEON_PRIM_TYPE_LINE_STRIP		(3 << 0)
-#define RADEON_PRIM_TYPE_TRI_LIST		(4 << 0)
-#define RADEON_PRIM_TYPE_TRI_FAN		(5 << 0)
-#define RADEON_PRIM_TYPE_TRI_STRIP		(6 << 0)
-#define RADEON_PRIM_TYPE_TRI_TYPE2		(7 << 0)
-#define RADEON_PRIM_TYPE_RECT_LIST		(8 << 0)
-#define RADEON_PRIM_TYPE_3VRT_POINT_LIST	(9 << 0)
-#define RADEON_PRIM_TYPE_3VRT_LINE_LIST		(10 << 0)
-#define RADEON_PRIM_TYPE_MASK                   0xf
-#define RADEON_PRIM_WALK_IND			(1 << 4)
-#define RADEON_PRIM_WALK_LIST			(2 << 4)
-#define RADEON_PRIM_WALK_RING			(3 << 4)
-#define RADEON_COLOR_ORDER_BGRA			(0 << 6)
-#define RADEON_COLOR_ORDER_RGBA			(1 << 6)
-#define RADEON_MAOS_ENABLE			(1 << 7)
-#define RADEON_VTX_FMT_R128_MODE		(0 << 8)
-#define RADEON_VTX_FMT_RADEON_MODE		(1 << 8)
-#define RADEON_NUM_VERTICES_SHIFT		16
-
-#define RADEON_COLOR_FORMAT_CI8		2
-#define RADEON_COLOR_FORMAT_ARGB1555	3
-#define RADEON_COLOR_FORMAT_RGB565	4
-#define RADEON_COLOR_FORMAT_ARGB8888	6
-#define RADEON_COLOR_FORMAT_RGB332	7
-#define RADEON_COLOR_FORMAT_RGB8	9
-#define RADEON_COLOR_FORMAT_ARGB4444	15
-
-#define RADEON_TXFORMAT_I8		0
-#define RADEON_TXFORMAT_AI88		1
-#define RADEON_TXFORMAT_RGB332		2
-#define RADEON_TXFORMAT_ARGB1555	3
-#define RADEON_TXFORMAT_RGB565		4
-#define RADEON_TXFORMAT_ARGB4444	5
-#define RADEON_TXFORMAT_ARGB8888	6
-#define RADEON_TXFORMAT_RGBA8888	7
-
-/* Constants */
-#define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */
-
-#define RADEON_LAST_FRAME_REG		RADEON_SCRATCH_REG0
-#define RADEON_LAST_DISPATCH_REG	RADEON_SCRATCH_REG1
-#define RADEON_LAST_CLEAR_REG		RADEON_SCRATCH_REG2
-#define RADEON_LAST_DISPATCH		1
-
-#define RADEON_MAX_VB_AGE		0x7fffffff
-#define RADEON_MAX_VB_VERTS		(0xffff)
-
-#define RADEON_RING_HIGH_MARK		128
-
-
-#define RADEON_BASE(reg)	((unsigned long)(dev_priv->mmio->handle))
-#define RADEON_ADDR(reg)	(RADEON_BASE( reg ) + reg)
-
-#define RADEON_DEREF(reg)	*(volatile u32 *)RADEON_ADDR( reg )
-#ifdef __alpha__
-#define RADEON_READ(reg)	(_RADEON_READ((u32 *)RADEON_ADDR( reg )))
-static inline u32 _RADEON_READ(u32 *addr)
-{
-	DRM_OS_READMEMORYBARRIER;
-	return *(volatile u32 *)addr;
-}
-#define RADEON_WRITE(reg,val)						\
-do {									\
-	DRM_OS_WRITEMEMORYBARRIER;					\
-	RADEON_DEREF(reg) = val;					\
-} while (0)
-#else
-#define RADEON_READ(reg)	RADEON_DEREF( reg )
-#define RADEON_WRITE(reg, val)	do { RADEON_DEREF( reg ) = val; } while (0)
-#endif
-
-#define RADEON_DEREF8(reg)	*(volatile u8 *)RADEON_ADDR( reg )
-#ifdef __alpha__
-#define RADEON_READ8(reg)	_RADEON_READ8((u8 *)RADEON_ADDR( reg ))
-static inline u8 _RADEON_READ8(u8 *addr)
-{
-	DRM_OS_READMEMORYBARRIER;
-	return *(volatile u8 *)addr;
-}
-#define RADEON_WRITE8(reg,val)						\
-do {									\
-	DRM_OS_WRITEMEMORYBARRIER;					\
-	RADEON_DEREF8( reg ) = val;					\
-} while (0)
-#else
-#define RADEON_READ8(reg)	RADEON_DEREF8( reg )
-#define RADEON_WRITE8(reg, val)	do { RADEON_DEREF8( reg ) = val; } while (0)
-#endif
-
-#define RADEON_WRITE_PLL( addr, val )					\
-do {									\
-	RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX,				\
-		       ((addr) & 0x1f) | RADEON_PLL_WR_EN );		\
-	RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) );			\
-} while (0)
-
-extern int RADEON_READ_PLL( drm_device_t *dev, int addr );
-
-
-#define CP_PACKET0( reg, n )						\
-	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
-#define CP_PACKET0_TABLE( reg, n )					\
-	(RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
-#define CP_PACKET1( reg0, reg1 )					\
-	(RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
-#define CP_PACKET2()							\
-	(RADEON_CP_PACKET2)
-#define CP_PACKET3( pkt, n )						\
-	(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
-
-
-/* ================================================================
- * Engine control helper macros
- */
-
-#define RADEON_WAIT_UNTIL_2D_IDLE() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_3D_IDLE() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_IDLE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |				\
-		   RADEON_WAIT_3D_IDLECLEAN |				\
-		   RADEON_WAIT_HOST_IDLECLEAN) );			\
-} while (0)
-
-#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do {				\
-	OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );			\
-	OUT_RING( RADEON_WAIT_CRTC_PFLIP );				\
-} while (0)
-
-#define RADEON_FLUSH_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB2D_DC_FLUSH );				\
-} while (0)
-
-#define RADEON_PURGE_CACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB2D_DSTCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB2D_DC_FLUSH_ALL );				\
-} while (0)
-
-#define RADEON_FLUSH_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH );				\
-} while (0)
-
-#define RADEON_PURGE_ZCACHE() do {					\
-	OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) );	\
-	OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL );				\
-} while (0)
-
-
-/* ================================================================
- * Misc helper macros
- */
-
-#define LOCK_TEST_WITH_RETURN( dev )					\
-do {									\
-	if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) ||		\
-	     dev->lock.pid != DRM_OS_CURRENTPID ) {				\
-		DRM_ERROR( "%s called without lock held\n",		\
-			   __FUNCTION__ );				\
-		DRM_OS_RETURN( EINVAL );						\
-	}								\
-} while (0)
-
-#define RING_SPACE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_radeon_ring_buffer_t *ring = &dev_priv->ring; int i;	\
-	if ( ring->space < ring->high_mark ) {				\
-		for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {	\
-			radeon_update_ring_snapshot( ring );		\
-			if ( ring->space >= ring->high_mark )		\
-				goto __ring_space_done;			\
-			DRM_OS_DELAY( 1 );					\
-		}							\
-		DRM_ERROR( "ring space check failed!\n" );		\
-		DRM_OS_RETURN( EBUSY );						\
-	}								\
- __ring_space_done:							\
-} while (0)
-
-#define VB_AGE_TEST_WITH_RETURN( dev_priv )				\
-do {									\
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
-	if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {		\
-		int __ret = radeon_do_cp_idle( dev_priv );		\
-		if ( __ret ) return __ret;				\
-		sarea_priv->last_dispatch = 0;				\
-		radeon_freelist_reset( dev );				\
-	}								\
-} while (0)
-
-#define RADEON_DISPATCH_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-#define RADEON_FRAME_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-#define RADEON_CLEAR_AGE( age ) do {					\
-	OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );		\
-	OUT_RING( age );						\
-} while (0)
-
-
-/* ================================================================
- * Ring control
- */
-
-#define radeon_flush_write_combine()	DRM_OS_READMEMORYBARRIER
-
-
-#define RADEON_VERBOSE	0
-
-#define RING_LOCALS	int write; unsigned int mask; volatile u32 *ring;
-
-#define BEGIN_RING( n ) do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "BEGIN_RING( %d ) in %s\n",			\
-			   n, __FUNCTION__ );				\
-	}								\
-	if ( dev_priv->ring.space <= (n) * sizeof(u32) ) {		\
-		radeon_wait_ring( dev_priv, (n) * sizeof(u32) );	\
-	}								\
-	dev_priv->ring.space -= (n) * sizeof(u32);			\
-	ring = dev_priv->ring.start;					\
-	write = dev_priv->ring.tail;					\
-	mask = dev_priv->ring.tail_mask;				\
-} while (0)
-
-#define ADVANCE_RING() do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n",	\
-			  write, dev_priv->ring.tail );			\
-	}								\
-	radeon_flush_write_combine();					\
-	dev_priv->ring.tail = write;					\
-	RADEON_WRITE( RADEON_CP_RB_WPTR, write );			\
-} while (0)
-
-#define OUT_RING( x ) do {						\
-	if ( RADEON_VERBOSE ) {						\
-		DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",		\
-			   (unsigned int)(x), write );			\
-	}								\
-	ring[write++] = (x);						\
-	write &= mask;							\
-} while (0)
-
-#define OUT_RING_REG( reg, val ) do {					\
-	OUT_RING( CP_PACKET0( reg, 0 ) );				\
-	OUT_RING( val );						\
-} while (0)
-
-#define RADEON_PERFORMANCE_BOXES	0
-
-#endif /* __RADEON_DRV_H__ */
diff --git a/bsd/radeon/radeon_state.c b/bsd/radeon/radeon_state.c
deleted file mode 100644
index cbb9d1f6..00000000
--- a/bsd/radeon/radeon_state.c
+++ /dev/null
@@ -1,1566 +0,0 @@
-/* radeon_state.c -- State support for Radeon -*- linux-c -*-
- *
- * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *    Gareth Hughes <gareth@valinux.com>
- *    Kevin E. Martin <martin@valinux.com>
- */
-
-#include "radeon.h"
-#include "drmP.h"
-#include "drm.h"
-#include "radeon_drm.h"
-#include "radeon_drv.h"
-
-
-/* ================================================================
- * CP hardware state programming functions
- */
-
-static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
-					  drm_clip_rect_t *box )
-{
-	RING_LOCALS;
-
-	DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
-		   box->x1, box->y1, box->x2, box->y2 );
-
-	BEGIN_RING( 4 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
-	OUT_RING( (box->y1 << 16) | box->x1 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
-	OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_context( drm_radeon_private_t *dev_priv,
- 					drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 14 );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
-	OUT_RING( ctx->pp_misc );
-	OUT_RING( ctx->pp_fog_color );
-	OUT_RING( ctx->re_solid_color );
-	OUT_RING( ctx->rb3d_blendcntl );
-	OUT_RING( ctx->rb3d_depthoffset );
-	OUT_RING( ctx->rb3d_depthpitch );
-	OUT_RING( ctx->rb3d_zstencilcntl );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
-	OUT_RING( ctx->pp_cntl );
-	OUT_RING( ctx->rb3d_cntl );
-	OUT_RING( ctx->rb3d_coloroffset );
-
-	OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
-	OUT_RING( ctx->rb3d_colorpitch );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_vertfmt( drm_radeon_private_t *dev_priv,
-					drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
-	OUT_RING( ctx->se_coord_fmt );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_line( drm_radeon_private_t *dev_priv,
-					drm_radeon_context_regs_t *ctx )
-{
-  	RING_LOCALS;
-/*  	printk( "    %s %x %x %x\n", __FUNCTION__,  */
-/*  		ctx->re_line_pattern, */
-/*  		ctx->re_line_state, */
-/*  		ctx->se_line_width); */
-
-	BEGIN_RING( 5 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
-	OUT_RING( ctx->re_line_pattern );
-	OUT_RING( ctx->re_line_state );
-
-	OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
-	OUT_RING( ctx->se_line_width );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_bumpmap( drm_radeon_private_t *dev_priv,
-					drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 5 );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
-	OUT_RING( ctx->pp_lum_matrix );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
-	OUT_RING( ctx->pp_rot_matrix_0 );
-	OUT_RING( ctx->pp_rot_matrix_1 );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_masks( drm_radeon_private_t *dev_priv,
-				      drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 4 );
-
-	OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
-	OUT_RING( ctx->rb3d_stencilrefmask );
-	OUT_RING( ctx->rb3d_ropcntl );
-	OUT_RING( ctx->rb3d_planemask );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_viewport( drm_radeon_private_t *dev_priv,
-					 drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 7 );
-
-	OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
-	OUT_RING( ctx->se_vport_xscale );
-	OUT_RING( ctx->se_vport_xoffset );
-	OUT_RING( ctx->se_vport_yscale );
-	OUT_RING( ctx->se_vport_yoffset );
-	OUT_RING( ctx->se_vport_zscale );
-	OUT_RING( ctx->se_vport_zoffset );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_setup( drm_radeon_private_t *dev_priv,
-				      drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 4 );
-
-	OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
-	OUT_RING( ctx->se_cntl );
-	OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
-	OUT_RING( ctx->se_cntl_status );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_misc( drm_radeon_private_t *dev_priv,
-				     drm_radeon_context_regs_t *ctx )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 2 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
-	OUT_RING( ctx->re_misc );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_tex0( drm_radeon_private_t *dev_priv,
-				     drm_radeon_texture_regs_t *tex )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
-
-	BEGIN_RING( 9 );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
-	OUT_RING( tex->pp_txfilter );
-	OUT_RING( tex->pp_txformat );
-	OUT_RING( tex->pp_txoffset );
-	OUT_RING( tex->pp_txcblend );
-	OUT_RING( tex->pp_txablend );
-	OUT_RING( tex->pp_tfactor );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
-	OUT_RING( tex->pp_border_color );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_tex1( drm_radeon_private_t *dev_priv,
-				     drm_radeon_texture_regs_t *tex )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s: offset=0x%x\n", __FUNCTION__, tex->pp_txoffset );
-
-	BEGIN_RING( 9 );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
-	OUT_RING( tex->pp_txfilter );
-	OUT_RING( tex->pp_txformat );
-	OUT_RING( tex->pp_txoffset );
-	OUT_RING( tex->pp_txcblend );
-	OUT_RING( tex->pp_txablend );
-	OUT_RING( tex->pp_tfactor );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
-	OUT_RING( tex->pp_border_color );
-
-	ADVANCE_RING();
-}
-
-static __inline__ void radeon_emit_tex2( drm_radeon_private_t *dev_priv,
-				     drm_radeon_texture_regs_t *tex )
-{
-	RING_LOCALS;
-	DRM_DEBUG( "    %s\n", __FUNCTION__ );
-
-	BEGIN_RING( 9 );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
-	OUT_RING( tex->pp_txfilter );
-	OUT_RING( tex->pp_txformat );
-	OUT_RING( tex->pp_txoffset );
-	OUT_RING( tex->pp_txcblend );
-	OUT_RING( tex->pp_txablend );
-	OUT_RING( tex->pp_tfactor );
-
-	OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
-	OUT_RING( tex->pp_border_color );
-
-	ADVANCE_RING();
-}
-
-#if 0
-static void radeon_print_dirty( const char *msg, unsigned int flags )
-{
-	DRM_DEBUG( "%s: (0x%x) %s%s%s%s%s%s%s%s%s%s%s%s%s\n",
-		   msg,
-		   flags,
- 		   (flags & RADEON_UPLOAD_CONTEXT)     ? "context, " : "",
- 		   (flags & RADEON_UPLOAD_VERTFMT)     ? "vertfmt, " : "",
- 		   (flags & RADEON_UPLOAD_LINE)        ? "line, " : "",
- 		   (flags & RADEON_UPLOAD_BUMPMAP)     ? "bumpmap, " : "",
- 		   (flags & RADEON_UPLOAD_MASKS)       ? "masks, " : "",
- 		   (flags & RADEON_UPLOAD_VIEWPORT)    ? "viewport, " : "",
- 		   (flags & RADEON_UPLOAD_SETUP)       ? "setup, " : "",
- 		   (flags & RADEON_UPLOAD_MISC)        ? "misc, " : "",
- 		   (flags & RADEON_UPLOAD_TEX0)        ? "tex0, " : "",
- 		   (flags & RADEON_UPLOAD_TEX1)        ? "tex1, " : "",
- 		   (flags & RADEON_UPLOAD_TEX2)        ? "tex2, " : "",
- 		   (flags & RADEON_UPLOAD_CLIPRECTS)   ? "cliprects, " : "",
- 		   (flags & RADEON_REQUIRE_QUIESCENCE) ? "quiescence, " : "" );
-}
-#endif
-  
-static __inline__ void radeon_emit_state( drm_radeon_private_t *dev_priv,
-				      drm_radeon_context_regs_t *ctx,
-				      drm_radeon_texture_regs_t *tex,
-				      unsigned int dirty )
-{
-  	DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
-  
-  	if ( dirty & RADEON_UPLOAD_CONTEXT ) {
- 		radeon_emit_context( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_VERTFMT ) {
- 		radeon_emit_vertfmt( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_LINE ) {
- 		radeon_emit_line( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
- 		radeon_emit_bumpmap( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_MASKS ) {
- 		radeon_emit_masks( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
- 		radeon_emit_viewport( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_SETUP ) {
- 		radeon_emit_setup( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_MISC ) {
- 		radeon_emit_misc( dev_priv, ctx );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_TEX0 ) {
- 		radeon_emit_tex0( dev_priv, &tex[0] );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_TEX1 ) {
- 		radeon_emit_tex1( dev_priv, &tex[1] );
-  	}
-  
-  	if ( dirty & RADEON_UPLOAD_TEX2 ) {
- 		radeon_emit_tex2( dev_priv, &tex[2] );
-  	}
-}
- 
- 
-static __inline__ void radeon_emit_zbias( drm_radeon_private_t *dev_priv,
-				      drm_radeon_context2_regs_t *ctx )
-{
- 	RING_LOCALS;
-/*  	printk( "    %s %x %x\n", __FUNCTION__, */
-/*  		ctx->se_zbias_factor, */
-/*  		ctx->se_zbias_constant ); */
- 
- 	BEGIN_RING( 3 );
- 	OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
-   	OUT_RING( ctx->se_zbias_factor ); 
-   	OUT_RING( ctx->se_zbias_constant ); 
- 	ADVANCE_RING();
-}
-  
-static __inline__ void radeon_emit_state2( drm_radeon_private_t *dev_priv,
-				       drm_radeon_state_t *state )
-{
- 	if (state->dirty & RADEON_UPLOAD_ZBIAS)
- 		radeon_emit_zbias( dev_priv, &state->context2 );
- 
- 	radeon_emit_state( dev_priv, &state->context, 
- 			   state->tex, state->dirty );
-}
- 
-#if RADEON_PERFORMANCE_BOXES
-/* ================================================================
- * Performance monitoring functions
- */
-
-static void radeon_clear_box( drm_radeon_private_t *dev_priv,
-			      int x, int y, int w, int h,
-			      int r, int g, int b )
-{
-	u32 pitch, offset;
-	u32 color;
-	RING_LOCALS;
-
-	switch ( dev_priv->color_fmt ) {
-	case RADEON_COLOR_FORMAT_RGB565:
-		color = (((r & 0xf8) << 8) |
-			 ((g & 0xfc) << 3) |
-			 ((b & 0xf8) >> 3));
-		break;
-	case RADEON_COLOR_FORMAT_ARGB8888:
-	default:
-		color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
-		break;
-	}
-
-	offset = dev_priv->back_offset;
-	pitch = dev_priv->back_pitch >> 3;
-
-	BEGIN_RING( 6 );
-
-	OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-	OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-		  RADEON_GMC_BRUSH_SOLID_COLOR |
-		  (dev_priv->color_fmt << 8) |
-		  RADEON_GMC_SRC_DATATYPE_COLOR |
-		  RADEON_ROP3_P |
-		  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-	OUT_RING( (pitch << 22) | (offset >> 5) );
-	OUT_RING( color );
-
-	OUT_RING( (x << 16) | y );
-	OUT_RING( (w << 16) | h );
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
-{
-	if ( atomic_read( &dev_priv->idle_count ) == 0 ) {
-		radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
-	} else {
-		atomic_set( &dev_priv->idle_count, 0 );
-	}
-}
-
-#endif
-
-
-/* ================================================================
- * CP command dispatch functions
- */
-
-static void radeon_cp_dispatch_clear( drm_device_t *dev,
-				      drm_radeon_clear_t *clear,
-				      drm_radeon_clear_rect_t *depth_boxes )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	unsigned int flags = clear->flags;
-	u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( __FUNCTION__": flags = 0x%x\n", flags );
-
-	if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
-		unsigned int tmp = flags;
-
-		flags &= ~(RADEON_FRONT | RADEON_BACK);
-		if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
-		if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
-	}
-
-	/* We have to clear the depth and/or stencil buffers by
-	 * rendering a quad into just those buffers.  Thus, we have to
-	 * make sure the 3D engine is configured correctly.
-	 */
-	if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) {
-		rb3d_cntl = depth_clear->rb3d_cntl;
-
-		if ( flags & RADEON_DEPTH ) {
-			rb3d_cntl |=  RADEON_Z_ENABLE;
-		} else {
-			rb3d_cntl &= ~RADEON_Z_ENABLE;
-		}
-
-		if ( flags & RADEON_STENCIL ) {
-			rb3d_cntl |=  RADEON_STENCIL_ENABLE;
-			rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
-		} else {
-			rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
-			rb3d_stencilrefmask = 0x00000000;
-		}
-	}
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
-			   x, y, w, h, flags );
-
-		if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
-			BEGIN_RING( 4 );
-
-			/* Ensure the 3D stream is idle before doing a
-			 * 2D fill to clear the front or back buffer.
-			 */
-			RADEON_WAIT_UNTIL_3D_IDLE();
-
-			OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
-			OUT_RING( clear->color_mask );
-
-			ADVANCE_RING();
-
-			/* Make sure we restore the 3D state next time.
-			 */
-			dev_priv->sarea_priv->ctx_owner = 0;
-		}
-
-		if ( flags & RADEON_FRONT ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-				  RADEON_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  RADEON_GMC_SRC_DATATYPE_COLOR |
-				  RADEON_ROP3_P |
-				  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-			OUT_RING( dev_priv->front_pitch_offset );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & RADEON_BACK ) {
-			BEGIN_RING( 6 );
-
-			OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
-			OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-				  RADEON_GMC_BRUSH_SOLID_COLOR |
-				  (dev_priv->color_fmt << 8) |
-				  RADEON_GMC_SRC_DATATYPE_COLOR |
-				  RADEON_ROP3_P |
-				  RADEON_GMC_CLR_CMP_CNTL_DIS );
-
-			OUT_RING( dev_priv->back_pitch_offset );
-			OUT_RING( clear->clear_color );
-
-			OUT_RING( (x << 16) | y );
-			OUT_RING( (w << 16) | h );
-
-			ADVANCE_RING();
-		}
-
-		if ( flags & (RADEON_DEPTH | RADEON_STENCIL) ) {
-
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-
-			BEGIN_RING( 25 );
-
-			RADEON_WAIT_UNTIL_2D_IDLE();
-
-			OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
-			OUT_RING( 0x00000000 );
-			OUT_RING( rb3d_cntl );
-
-			OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
-				      depth_clear->rb3d_zstencilcntl );
-			OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
-				      rb3d_stencilrefmask );
-			OUT_RING_REG( RADEON_RB3D_PLANEMASK,
-				      0x00000000 );
-			OUT_RING_REG( RADEON_SE_CNTL,
-				      depth_clear->se_cntl );
-
-			OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 10 ) );
-			OUT_RING( RADEON_VTX_Z_PRESENT );
-			OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
-				   RADEON_PRIM_WALK_RING |
-				   RADEON_MAOS_ENABLE |
-				   RADEON_VTX_FMT_RADEON_MODE |
-				   (3 << RADEON_NUM_VERTICES_SHIFT)) );
-
-/*  			printk( "depth box %d: %x %x %x %x\n",  */
-/*  				i, */
-/*  				depth_boxes[i].ui[CLEAR_X1], */
-/*  				depth_boxes[i].ui[CLEAR_Y1], */
-/*  				depth_boxes[i].ui[CLEAR_X2], */
-/*  				depth_boxes[i].ui[CLEAR_Y2]); */
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-
-			OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
-			OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
-
-			ADVANCE_RING();
-
-			/* Make sure we restore the 3D state next time.
-			 */
-			dev_priv->sarea_priv->ctx_owner = 0;
-		}
-	}
-
-	/* Increment the clear counter.  The client-side 3D driver must
-	 * wait on this value before performing the clear ioctl.  We
-	 * need this because the card's so damned fast...
-	 */
-	dev_priv->sarea_priv->last_clear++;
-
-	BEGIN_RING( 4 );
-
-	RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_dispatch_swap( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int nbox = sarea_priv->nbox;
-	drm_clip_rect_t *pbox = sarea_priv->boxes;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-#if RADEON_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	radeon_cp_performance_boxes( dev_priv );
-#endif
-
-	/* Wait for the 3D stream to idle before dispatching the bitblt.
-	 * This will prevent data corruption between the two streams.
-	 */
-	BEGIN_RING( 2 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
-	ADVANCE_RING();
-
-	for ( i = 0 ; i < nbox ; i++ ) {
-		int x = pbox[i].x1;
-		int y = pbox[i].y1;
-		int w = pbox[i].x2 - x;
-		int h = pbox[i].y2 - y;
-
-		DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
-			   x, y, w, h );
-
-		BEGIN_RING( 7 );
-
-		OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
-		OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-			  RADEON_GMC_BRUSH_NONE |
-			  (dev_priv->color_fmt << 8) |
-			  RADEON_GMC_SRC_DATATYPE_COLOR |
-			  RADEON_ROP3_S |
-			  RADEON_DP_SRC_SOURCE_MEMORY |
-			  RADEON_GMC_CLR_CMP_CNTL_DIS |
-			  RADEON_GMC_WR_MSK_DIS );
-
-		OUT_RING( dev_priv->back_pitch_offset );
-		OUT_RING( dev_priv->front_pitch_offset );
-
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (x << 16) | y );
-		OUT_RING( (w << 16) | h );
-
-		ADVANCE_RING();
-	}
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 4 );
-
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
-	RADEON_WAIT_UNTIL_2D_IDLE();
-
-	ADVANCE_RING();
-}
-
-static void radeon_cp_dispatch_flip( drm_device_t *dev )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "%s: page=%d\n", __FUNCTION__, dev_priv->current_page );
-
-#if RADEON_PERFORMANCE_BOXES
-	/* Do some trivial performance monitoring...
-	 */
-	radeon_cp_performance_boxes( dev_priv );
-#endif
-
-	BEGIN_RING( 6 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-	RADEON_WAIT_UNTIL_PAGE_FLIPPED();
-
-	OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET, 0 ) );
-
-	if ( dev_priv->current_page == 0 ) {
-		OUT_RING( dev_priv->back_offset );
-		dev_priv->current_page = 1;
-	} else {
-		OUT_RING( dev_priv->front_offset );
-		dev_priv->current_page = 0;
-	}
-
-	ADVANCE_RING();
-
-	/* Increment the frame counter.  The client-side 3D driver must
-	 * throttle the framerate by waiting for this value before
-	 * performing the swapbuffer ioctl.
-	 */
-	dev_priv->sarea_priv->last_frame++;
-
-	BEGIN_RING( 2 );
-
-	RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
-
-	ADVANCE_RING();
-}
-
-
-static void radeon_cp_dispatch_vertex( drm_device_t *dev,
-				       drm_buf_t *buf,
-				       drm_radeon_prim_t *prim )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-	int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
-	int numverts = (int)prim->numverts;
-	int i = 0;
-	RING_LOCALS;
-
-	DRM_DEBUG( __FUNCTION__": nbox=%d %d..%d prim %x nvert %d\n",
-		   sarea_priv->nbox, prim->start, prim->finish,
-		   prim->prim, numverts );
-
-	buf_priv->dispatched = 1;
-
-	do {
-		/* Emit the next cliprect */
-		if ( i < sarea_priv->nbox ) {
-			radeon_emit_clip_rect( dev_priv,
-					       &sarea_priv->boxes[i] );
-		}
-
-		/* Emit the vertex buffer rendering commands */
-		BEGIN_RING( 5 );
-
-		OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
-		OUT_RING( offset );
-		OUT_RING( numverts );
-		OUT_RING( prim->vc_format );
-		OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
-			  RADEON_COLOR_ORDER_RGBA |
-			  RADEON_VTX_FMT_RADEON_MODE |
-			  (numverts << RADEON_NUM_VERTICES_SHIFT) );
-
-		ADVANCE_RING();
-
-		i++;
-	} while ( i < sarea_priv->nbox );
-
-	dev_priv->sarea_priv->last_dispatch++;
-}
-
-
-static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-	RING_LOCALS;
-
-	buf_priv->age = dev_priv->sarea_priv->last_dispatch;
-
-	/* Emit the vertex buffer age */
-	BEGIN_RING( 2 );
-	RADEON_DISPATCH_AGE( buf_priv->age );
-	ADVANCE_RING();
-
-	buf->pending = 1;
-	buf->used = 0;
-	/* FIXME: Check dispatched field */
-	buf_priv->dispatched = 0;
-}
-
-static void radeon_cp_dispatch_indirect( drm_device_t *dev,
-					 drm_buf_t *buf,
-					 int start, int end )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
-	RING_LOCALS;
-	DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
-		   buf->idx, start, end );
-
-	if ( start != end ) {
-		int offset = (dev_priv->agp_buffers_offset
-			      + buf->offset + start);
-		int dwords = (end - start + 3) / sizeof(u32);
-
-		/* Indirect buffer data must be an even number of
-		 * dwords, so if we've been given an odd number we must
-		 * pad the data with a Type-2 CP packet.
-		 */
-		if ( dwords & 1 ) {
-			u32 *data = (u32 *)
-				((char *)dev_priv->buffers->handle
-				 + buf->offset + start);
-			data[dwords++] = RADEON_CP_PACKET2;
-		}
-
-		buf_priv->dispatched = 1;
-
-		/* Fire off the indirect buffer */
-		BEGIN_RING( 3 );
-
-		OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
-		OUT_RING( offset );
-		OUT_RING( dwords );
-
-		ADVANCE_RING();
-	}
-
-	dev_priv->sarea_priv->last_dispatch++;
-}
-
-static void radeon_cp_dispatch_indices( drm_device_t *dev,
-					drm_buf_t *elt_buf,
-					drm_radeon_prim_t *prim )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_buf_priv_t *buf_priv = elt_buf->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int offset = dev_priv->agp_buffers_offset + prim->numverts * 64;
-	u32 *data;
-	int dwords;
-	int i = 0;
-	int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
-	int count = (prim->finish - start) / sizeof(u16);
-
-  	DRM_DEBUG( "indices: start=%x/%x end=%x count=%d nv %d offset %x\n",
-		   prim->start, start, prim->finish,
-		   count, prim->numverts, offset );
-
-	if ( start < prim->finish ) {
-		buf_priv->dispatched = 1;
-
-		dwords = (prim->finish - prim->start + 3) / sizeof(u32);
-
-		data = (u32 *)((char *)dev_priv->buffers->handle +
-			       elt_buf->offset + prim->start);
-
-		data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
-		data[1] = offset;
-		data[2] = RADEON_MAX_VB_VERTS;
-		data[3] = prim->vc_format;
-		data[4] = (prim->prim |
-			   RADEON_PRIM_WALK_IND |
-			   RADEON_COLOR_ORDER_RGBA |
-			   RADEON_VTX_FMT_RADEON_MODE |
-			   (count << RADEON_NUM_VERTICES_SHIFT) );
-
-		if ( count & 0x1 ) {
-			/* unnecessary? */
-			data[dwords-1] &= 0x0000ffff;
-		}
-
-		do {
-			/* Emit the next set of up to three cliprects */
-			if ( i < sarea_priv->nbox ) {
-				radeon_emit_clip_rect( dev_priv,
-						       &sarea_priv->boxes[i] );
-			}
-
-			radeon_cp_dispatch_indirect( dev, elt_buf,
-						     prim->start,
-						     prim->finish );
-
-			i++;
-		} while ( i < sarea_priv->nbox );
-	}
-
-	sarea_priv->last_dispatch++;
-}
-
-#define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
-
-static int radeon_cp_dispatch_texture( drm_device_t *dev,
-				       drm_radeon_texture_t *tex,
-				       drm_radeon_tex_image_t *image, int pid )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	u32 format;
-	u32 *buffer;
-	const u8 *data;
-	int size, dwords, tex_width, blit_width;
-	u32 y, height;
-	int ret = 0, i;
-	RING_LOCALS;
-
-	/* FIXME: Be smarter about this...
-	 */
-	buf = radeon_freelist_get( dev );
-	if ( !buf ) DRM_OS_RETURN( EAGAIN );
-
-	DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
-		   tex->offset >> 10, tex->pitch, tex->format,
-		   image->x, image->y, image->width, image->height );
-
-	buf_priv = buf->dev_private;
-
-	/* The compiler won't optimize away a division by a variable,
-	 * even if the only legal values are powers of two.  Thus, we'll
-	 * use a shift instead.
-	 */
-	switch ( tex->format ) {
-	case RADEON_TXFORMAT_ARGB8888:
-	case RADEON_TXFORMAT_RGBA8888:
-		format = RADEON_COLOR_FORMAT_ARGB8888;
-		tex_width = tex->width * 4;
-		blit_width = image->width * 4;
-		break;
-	case RADEON_TXFORMAT_AI88:
-	case RADEON_TXFORMAT_ARGB1555:
-	case RADEON_TXFORMAT_RGB565:
-	case RADEON_TXFORMAT_ARGB4444:
-		format = RADEON_COLOR_FORMAT_RGB565;
-		tex_width = tex->width * 2;
-		blit_width = image->width * 2;
-		break;
-	case RADEON_TXFORMAT_I8:
-	case RADEON_TXFORMAT_RGB332:
-		format = RADEON_COLOR_FORMAT_CI8;
-		tex_width = tex->width * 1;
-		blit_width = image->width * 1;
-		break;
-	default:
-		DRM_ERROR( "invalid texture format %d\n", tex->format );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_DEBUG( "   tex=%dx%d  blit=%d\n",
-		   tex_width, tex->height, blit_width );
-
-	/* Flush the pixel cache.  This ensures no pixel data gets mixed
-	 * up with the texture data from the host data blit, otherwise
-	 * part of the texture image may be corrupted.
-	 */
-	BEGIN_RING( 4 );
-
-	RADEON_FLUSH_CACHE();
-	RADEON_WAIT_UNTIL_IDLE();
-
-	ADVANCE_RING();
-
-	/* Make a copy of the parameters in case we have to update them
-	 * for a multi-pass texture blit.
-	 */
-	y = image->y;
-	height = image->height;
-	data = image->data;
-
-	size = height * blit_width;
-
-	if ( size > RADEON_MAX_TEXTURE_SIZE ) {
-		/* Texture image is too large, do a multipass upload */
-		ret = EAGAIN;
-
-		/* Adjust the blit size to fit the indirect buffer */
-		height = RADEON_MAX_TEXTURE_SIZE / blit_width;
-		size = height * blit_width;
-
-		/* Update the input parameters for next time */
-		image->y += height;
-		image->height -= height;
-		image->data = (const char *)image->data + size;
-
-		if ( DRM_OS_COPYTOUSR( tex->image, image, sizeof(*image) ) ) {
-			DRM_ERROR( "EFAULT on tex->image\n" );
-			DRM_OS_RETURN( EFAULT );
-		}
-	} else if ( size < 4 ) {
-		size = 4;
-	}
-
-	dwords = size / 4;
-
-	/* Dispatch the indirect buffer.
-	 */
-	buffer = (u32 *)((char *)dev_priv->buffers->handle + buf->offset);
-
-	buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
-	buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
-		     RADEON_GMC_BRUSH_NONE |
-		     (format << 8) |
-		     RADEON_GMC_SRC_DATATYPE_COLOR |
-		     RADEON_ROP3_S |
-		     RADEON_DP_SRC_SOURCE_HOST_DATA |
-		     RADEON_GMC_CLR_CMP_CNTL_DIS |
-		     RADEON_GMC_WR_MSK_DIS);
-
-	buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
-	buffer[3] = 0xffffffff;
-	buffer[4] = 0xffffffff;
-	buffer[5] = (y << 16) | image->x;
-	buffer[6] = (height << 16) | image->width;
-	buffer[7] = dwords;
-
-	buffer += 8;
-
-	if ( tex_width >= 32 ) {
-		/* Texture image width is larger than the minimum, so we
-		 * can upload it directly.
-		 */
-		if ( DRM_OS_COPYFROMUSR( buffer, data, dwords * sizeof(u32) ) ) {
-			DRM_ERROR( "EFAULT on data, %d dwords\n", dwords );
-			DRM_OS_RETURN( EFAULT );
-		}
-	} else {
-		/* Texture image width is less than the minimum, so we
-		 * need to pad out each image scanline to the minimum
-		 * width.
-		 */
-		for ( i = 0 ; i < tex->height ; i++ ) {
-			if ( DRM_OS_COPYFROMUSR( buffer, data, tex_width ) ) {
-				DRM_ERROR( "EFAULT on pad, %d bytes\n",
-					   tex_width );
-				DRM_OS_RETURN( EFAULT );
-			}
-			buffer += 8;
-			data += tex_width;
-		}
-	}
-
-	buf->pid = pid;
-	buf->used = (dwords + 8) * sizeof(u32);
-	buf_priv->discard = 1;
-
-	radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
-	radeon_cp_discard_buffer( dev, buf );
-
-	/* Flush the pixel cache after the blit completes.  This ensures
-	 * the texture data is written out to memory before rendering
-	 * continues.
-	 */
-	BEGIN_RING( 4 );
-
-	RADEON_FLUSH_CACHE();
-	RADEON_WAIT_UNTIL_2D_IDLE();
-
-	ADVANCE_RING();
-
-	DRM_OS_RETURN( ret );
-}
-
-static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
-{
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	int i;
-	RING_LOCALS;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	BEGIN_RING( 35 );
-
-	OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
-	OUT_RING( 0x00000000 );
-
-	OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
-	for ( i = 0 ; i < 32 ; i++ ) {
-		OUT_RING( stipple[i] );
-	}
-
-	ADVANCE_RING();
-}
-
-
-/* ================================================================
- * IOCTL functions
- */
-
-int radeon_cp_clear( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_radeon_clear_t clear;
-	drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( clear, (drm_radeon_clear_t *) data,
-			     sizeof(clear) );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
-
-	if ( DRM_OS_COPYFROMUSR( &depth_boxes, clear.depth_boxes,
-			     sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
-		DRM_OS_RETURN( EFAULT );
-
-	/* Needed for depth clears via triangles???
-	 */
-	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-		radeon_emit_state( dev_priv,
-				   &sarea_priv->context_state,
-				   sarea_priv->tex_state,
-				   sarea_priv->dirty );
-
-		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-				       RADEON_UPLOAD_TEX1IMAGES |
-				       RADEON_UPLOAD_TEX2IMAGES |
-				       RADEON_REQUIRE_QUIESCENCE);
-	}
-
-	radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
-
-	return 0;
-}
-
-int radeon_cp_swap( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	DRM_DEBUG( "%s\n", __FUNCTION__ );
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
-		sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
-
-	if ( !dev_priv->page_flipping ) {
-		radeon_cp_dispatch_swap( dev );
-		dev_priv->sarea_priv->ctx_owner = 0;
-	} else {
-		radeon_cp_dispatch_flip( dev );
-	}
-
-	return 0;
-}
-
-int radeon_cp_vertex( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_radeon_vertex_t vertex;
-	drm_radeon_prim_t prim;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_OS_KRNFROMUSR( vertex, (drm_radeon_vertex_t *) data,
-			     sizeof(vertex) );
-
-	DRM_DEBUG( "%s: pid=%d index=%d count=%d discard=%d\n",
-		   __FUNCTION__, DRM_OS_CURRENTPID,
-		   vertex.idx, vertex.count, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( vertex.prim < 0 ||
-	     vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", vertex.prim );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf->used = vertex.count; /* not used? */
-
-	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-		radeon_emit_state( dev_priv,
-				   &sarea_priv->context_state,
-				   sarea_priv->tex_state,
-				   sarea_priv->dirty );
-
-		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-				       RADEON_UPLOAD_TEX1IMAGES |
-				       RADEON_UPLOAD_TEX2IMAGES |
-				       RADEON_REQUIRE_QUIESCENCE);
-	}
-
-	/* Build up a prim_t record:
-	 */
-	prim.start = 0;
-	prim.finish = vertex.count; /* unused */
-	prim.prim = vertex.prim;
-	prim.stateidx = 0xff;	/* unused */
-	prim.numverts = vertex.count;
-	prim.vc_format = dev_priv->sarea_priv->vc_format;
-	
-	radeon_cp_dispatch_vertex( dev, buf, &prim );
-	if (vertex.discard) {
-	   radeon_cp_discard_buffer( dev, buf );
-	}
-
-	return 0;
-}
-
-int radeon_cp_indices( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_radeon_indices_t elts;
-	drm_radeon_prim_t prim;
-	int count;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_OS_KRNFROMUSR( elts, (drm_radeon_indices_t *) data,
-			     sizeof(elts) );
-
-	DRM_DEBUG( "%s: pid=%d index=%d start=%d end=%d discard=%d\n",
-		   __FUNCTION__, DRM_OS_CURRENTPID,
-		   elts.idx, elts.start, elts.end, elts.discard );
-
-	if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   elts.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( elts.prim < 0 ||
-	     elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-		DRM_ERROR( "buffer prim %d\n", elts.prim );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[elts.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			  DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", elts.idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	count = (elts.end - elts.start) / sizeof(u16);
-	elts.start -= RADEON_INDEX_PRIM_OFFSET;
-
-	if ( elts.start & 0x7 ) {
-		DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( elts.start < buf->used ) {
-		DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf->used = elts.end;
-
-	if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
-		radeon_emit_state( dev_priv,
-				   &sarea_priv->context_state,
-				   sarea_priv->tex_state,
-				   sarea_priv->dirty );
-
-		sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
-				       RADEON_UPLOAD_TEX1IMAGES |
-				       RADEON_UPLOAD_TEX2IMAGES |
-				       RADEON_REQUIRE_QUIESCENCE);
-	}
-
-
-	/* Build up a prim_t record:
-	 */
-	prim.start = elts.start;
-	prim.finish = elts.end; /* unused */
-	prim.prim = elts.prim;
-	prim.stateidx = 0xff;	/* unused */
-	prim.numverts = count;
-	prim.vc_format = dev_priv->sarea_priv->vc_format;
-	
-	radeon_cp_dispatch_indices( dev, buf, &prim );
-	if (elts.discard) {
-	   radeon_cp_discard_buffer( dev, buf );
-	}
-
-	return 0;
-}
-
-int radeon_cp_texture( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_texture_t tex;
-	drm_radeon_tex_image_t image;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( tex, (drm_radeon_texture_t *) data, sizeof(tex) );
-
-	if ( tex.image == NULL ) {
-		DRM_ERROR( "null texture image!\n" );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if ( DRM_OS_COPYFROMUSR( &image,
-			     (drm_radeon_tex_image_t *)tex.image,
-			     sizeof(image) ) )
-		DRM_OS_RETURN( EFAULT );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	return radeon_cp_dispatch_texture( dev, &tex, &image, DRM_OS_CURRENTPID );
-}
-
-int radeon_cp_stipple( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_radeon_stipple_t stipple;
-	u32 mask[32];
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	DRM_OS_KRNFROMUSR( stipple, (drm_radeon_stipple_t *) data,
-			     sizeof(stipple) );
-
-	if ( DRM_OS_COPYFROMUSR( &mask, stipple.mask, 32 * sizeof(u32) ) )
-		DRM_OS_RETURN( EFAULT );
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-
-	radeon_cp_dispatch_stipple( dev, mask );
-
-	return 0;
-}
-
-int radeon_cp_indirect( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_radeon_indirect_t indirect;
-	RING_LOCALS;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	DRM_OS_KRNFROMUSR( indirect, (drm_radeon_indirect_t *) data,
-			     sizeof(indirect) );
-
-	DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
-		   indirect.idx, indirect.start,
-		   indirect.end, indirect.discard );
-
-	if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   indirect.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	buf = dma->buflist[indirect.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN( EINVAL );
-	}
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	if ( indirect.start < buf->used ) {
-		DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
-			   indirect.start, buf->used );
-		DRM_OS_RETURN( EINVAL );
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf->used = indirect.end;
-	buf_priv->discard = indirect.discard;
-
-	/* Wait for the 3D stream to idle before the indirect buffer
-	 * containing 2D acceleration commands is processed.
-	 */
-	BEGIN_RING( 2 );
-
-	RADEON_WAIT_UNTIL_3D_IDLE();
-
-	ADVANCE_RING();
-
-	/* Dispatch the indirect buffer full of commands from the
-	 * X server.  This is insecure and is thus only available to
-	 * privileged clients.
-	 */
-	radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
-	if (indirect.discard) {
-	   radeon_cp_discard_buffer( dev, buf );
-	}
-
-
-	return 0;
-}
-
-int radeon_cp_vertex2( DRM_OS_IOCTL )
-{
-	DRM_OS_DEVICE;
-	drm_radeon_private_t *dev_priv = dev->dev_private;
-	drm_device_dma_t *dma = dev->dma;
-	drm_buf_t *buf;
-	drm_radeon_buf_priv_t *buf_priv;
-	drm_radeon_vertex2_t vertex;
-	int i;
-	unsigned char laststate;
-
-	LOCK_TEST_WITH_RETURN( dev );
-
-	if ( !dev_priv ) {
-		DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	DRM_OS_KRNFROMUSR(vertex, (drm_radeon_vertex2_t *)data, sizeof(vertex));
-
-	DRM_DEBUG( __FUNCTION__": pid=%d index=%d discard=%d\n",
-		   current->pid, vertex.idx, vertex.discard );
-
-	if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
-		DRM_ERROR( "buffer index %d (of %d max)\n",
-			   vertex.idx, dma->buf_count - 1 );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	RING_SPACE_TEST_WITH_RETURN( dev_priv );
-	VB_AGE_TEST_WITH_RETURN( dev_priv );
-
-	buf = dma->buflist[vertex.idx];
-	buf_priv = buf->dev_private;
-
-	if ( buf->pid != DRM_OS_CURRENTPID ) {
-		DRM_ERROR( "process %d using buffer owned by %d\n",
-			   DRM_OS_CURRENTPID, buf->pid );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	if ( buf->pending ) {
-		DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
-		DRM_OS_RETURN(EINVAL);
-	}
-
-	for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
-		drm_radeon_prim_t prim;
-		
-		if ( DRM_OS_COPYFROMUSR( &prim, &vertex.prim[i], sizeof(prim)))
-			DRM_OS_RETURN(EINVAL);
-		
-/*    		printk( "prim %d vfmt %x hwprim %x start %d finish %d\n", */
-/*  			   i, prim.vc_format, prim.prim, */
-/*  			   prim.start, prim.finish ); */
-
-		if (  (prim.prim & RADEON_PRIM_TYPE_MASK) > 
-		      RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
-			DRM_ERROR( "buffer prim %d\n", prim.prim );
-			DRM_OS_RETURN(EINVAL);
-		}
-
-		if ( prim.stateidx != laststate ) {
-			drm_radeon_state_t state;			       
-				
-			if ( DRM_OS_COPYFROMUSR( &state,
-						 &vertex.state[prim.stateidx],
-						 sizeof(state) ) )
-				DRM_OS_RETURN(EINVAL);
-
-/*  			printk("emit state %d (%p) dirty %x\n", */
-/*  			       prim.stateidx, */
-/*  			       &vertex.state[prim.stateidx], */
-/*  			       state.dirty); */
-
-			radeon_emit_state2( dev_priv, &state );
-
-			laststate = prim.stateidx;
-		}
-
-		if ( prim.finish <= prim.start )
-			continue;
-
-		if ( prim.start & 0x7 ) {
-			DRM_ERROR( "misaligned buffer 0x%x\n", prim.start );
-			DRM_OS_RETURN(EINVAL);
-		}
-
-		if ( prim.prim & RADEON_PRIM_WALK_IND ) {
-			radeon_cp_dispatch_indices( dev, buf, &prim );
-		} else {
-			radeon_cp_dispatch_vertex( dev, buf, &prim );
-		}
-	}
-
-	if ( vertex.discard ) {
-		radeon_cp_discard_buffer( dev, buf );
-	}
-
-	return 0;
-}