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authorIan Romanick <idr@us.ibm.com>2007-08-09 18:15:42 -0700
committerIan Romanick <idr@us.ibm.com>2007-08-09 18:15:42 -0700
commit371f0a4d410f02d8db050b51fd2e714f888a71e0 (patch)
tree1fc0e8a7efeb8f3723e7dab31ef2b10a495c2f30 /linux-core/xgi_cmdlist.h
parent6dd97099ea5c6dc7931c6b482eb5935f7dd9ed2d (diff)
Mask off correct bits in M2REG_AUTO_LINK_STATUS for interrupt handling.
Diffstat (limited to 'linux-core/xgi_cmdlist.h')
-rw-r--r--linux-core/xgi_cmdlist.h29
1 files changed, 0 insertions, 29 deletions
diff --git a/linux-core/xgi_cmdlist.h b/linux-core/xgi_cmdlist.h
index 07a2eb98..dc3fbe5a 100644
--- a/linux-core/xgi_cmdlist.h
+++ b/linux-core/xgi_cmdlist.h
@@ -27,35 +27,6 @@
#ifndef _XGI_CMDLIST_H_
#define _XGI_CMDLIST_H_
-#define ONE_BIT_MASK 0x1
-#define TWENTY_BIT_MASK 0xfffff
-#define M2REG_FLUSH_2D_ENGINE_MASK (ONE_BIT_MASK<<20)
-#define M2REG_FLUSH_3D_ENGINE_MASK TWENTY_BIT_MASK
-#define M2REG_FLUSH_FLIP_ENGINE_MASK (ONE_BIT_MASK<<21)
-#define BASE_3D_ENG 0x2800
-#define M2REG_AUTO_LINK_SETTING_ADDRESS 0x10
-#define M2REG_CLEAR_COUNTERS_MASK (ONE_BIT_MASK<<4)
-#define M2REG_PCI_TRIGGER_MODE_MASK (ONE_BIT_MASK<<1)
-#define BEGIN_VALID_MASK (ONE_BIT_MASK<<20)
-#define BEGIN_LINK_ENABLE_MASK (ONE_BIT_MASK<<31)
-#define BEGIN_BEGIN_IDENTIFICATION_MASK (TWENTY_BIT_MASK<<0)
-#define M2REG_PCI_TRIGGER_REGISTER_ADDRESS 0x14
-
-typedef enum {
- FLUSH_2D = M2REG_FLUSH_2D_ENGINE_MASK,
- FLUSH_3D = M2REG_FLUSH_3D_ENGINE_MASK,
- FLUSH_FLIP = M2REG_FLUSH_FLIP_ENGINE_MASK
-} FLUSH_CODE;
-
-typedef enum {
- AGPCMDLIST_SCRATCH_SIZE = 0x100,
- AGPCMDLIST_BEGIN_SIZE = 0x004,
- AGPCMDLIST_3D_SCRATCH_CMD_SIZE = 0x004,
- AGPCMDLIST_2D_SCRATCH_CMD_SIZE = 0x00c,
- AGPCMDLIST_FLUSH_CMD_LEN = 0x004,
- AGPCMDLIST_DUMY_END_BATCH_LEN = AGPCMDLIST_BEGIN_SIZE
-} CMD_SIZE;
-
struct xgi_cmdring_info {
/**
* Kernel space pointer to the base of the command ring.