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authorBen Skeggs <skeggsb@gmail.com>2007-06-24 18:58:38 +1000
committerBen Skeggs <skeggsb@gmail.com>2007-06-24 18:58:38 +1000
commit5d55b0655cb480b7d6ab4cf2467dac6dc6d8df25 (patch)
treec65ffb5c821a183421512ebdf0de7ca7b66357d8 /shared-core/nv30_graph.c
parent341bc7820749024e09275de6e689b10c2908689a (diff)
nouveau: NV3X PGRAPH engtab functions
Diffstat (limited to 'shared-core/nv30_graph.c')
-rw-r--r--shared-core/nv30_graph.c66
1 files changed, 65 insertions, 1 deletions
diff --git a/shared-core/nv30_graph.c b/shared-core/nv30_graph.c
index f4faadd8..9f064a0a 100644
--- a/shared-core/nv30_graph.c
+++ b/shared-core/nv30_graph.c
@@ -100,7 +100,7 @@ static void nv30_graph_context_init(drm_device_t *dev, struct mem_block *ctx)
}
-int nv30_graph_context_create(drm_device_t *dev, int channel)
+int nv30_graph_create_context(drm_device_t *dev, int channel)
{
drm_nouveau_private_t *dev_priv =
(drm_nouveau_private_t *)dev->dev_private;
@@ -132,6 +132,70 @@ int nv30_graph_context_create(drm_device_t *dev, int channel)
return 0;
}
+void nv30_graph_destroy_context(drm_device_t *dev, int channel)
+{
+ drm_nouveau_private_t *dev_priv =
+ (drm_nouveau_private_t *)dev->dev_private;
+ struct nouveau_fifo *chan = &dev_priv->fifos[channel];
+
+ if (chan->ramin_grctx) {
+ nouveau_instmem_free(dev, chan->ramin_grctx);
+ chan->ramin_grctx = NULL;
+ }
+
+ INSTANCE_WR(dev_priv->ctx_table, channel, 0);
+}
+
+static int
+nouveau_graph_wait_idle(drm_device_t *dev)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ int tv = 1000;
+
+ while (tv--) {
+ if (NV_READ(0x400700) == 0)
+ break;
+ }
+
+ if (NV_READ(0x400700)) {
+ DRM_ERROR("timeout!\n");
+ return DRM_ERR(EBUSY);
+ }
+ return 0;
+}
+
+int nv30_graph_load_context(drm_device_t *dev, int channel)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ struct nouveau_fifo *chan = &dev_priv->fifos[channel];
+ uint32_t inst;
+
+ if (!chan->ramin_grctx)
+ return DRM_ERR(EINVAL);
+ inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
+
+ NV_WRITE(0x400784, inst);
+ NV_WRITE(0x400788, 1);
+
+ return nouveau_graph_wait_idle(dev);
+}
+
+int nv30_graph_save_context(drm_device_t *dev, int channel)
+{
+ drm_nouveau_private_t *dev_priv = dev->dev_private;
+ struct nouveau_fifo *chan = &dev_priv->fifos[channel];
+ uint32_t inst;
+
+ if (!chan->ramin_grctx)
+ return DRM_ERR(EINVAL);
+ inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
+
+ NV_WRITE(0x400784, inst);
+ NV_WRITE(0x400788, 2);
+
+ return nouveau_graph_wait_idle(dev);
+}
+
int nv30_graph_init(drm_device_t *dev)
{
drm_nouveau_private_t *dev_priv =