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authorDave Airlie <airlied@linux.ie>2007-03-04 18:13:34 +1100
committerDave Airlie <airlied@linux.ie>2007-03-04 18:16:29 +1100
commitc9178c3d01f6f38a33f9624c620d290cb9036964 (patch)
tree115ff3c53b8ab88f6eae0523e2674a1101bc82b2 /shared-core/radeon_cp.c
parent72caa48c82e4334d3292185dbadf758d2dd14c16 (diff)
ati: make pcigart code able to handle variable size PCI GART aperture
This code doesn't enable a variable aperture it just modifies the codebase to allow me fix it up later
Diffstat (limited to 'shared-core/radeon_cp.c')
-rw-r--r--shared-core/radeon_cp.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c
index 0fa6535d..976b9fbd 100644
--- a/shared-core/radeon_cp.c
+++ b/shared-core/radeon_cp.c
@@ -1622,6 +1622,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
} else
#endif
{
+ dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset) {
dev_priv->gart_info.bus_addr =
@@ -1629,7 +1630,7 @@ static int radeon_do_init_cp(drm_device_t * dev, drm_radeon_init_t * init)
dev_priv->gart_info.mapping.offset =
dev_priv->gart_info.bus_addr;
dev_priv->gart_info.mapping.size =
- RADEON_PCIGART_TABLE_SIZE;
+ dev_priv->gart_info.table_size;
drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
dev_priv->gart_info.addr =