diff options
| author | Michel Daenzer <michel@daenzer.net> | 2003-08-26 15:44:01 +0000 |
|---|---|---|
| committer | Michel Daenzer <michel@daenzer.net> | 2003-08-26 15:44:01 +0000 |
| commit | 062751ac472b2721bed0cd1ee48a3ae7d327ff07 (patch) | |
| tree | 8f06a7fe6f51e14d34bae4add2df854c6f6398c8 /shared-core/radeon_state.c | |
| parent | 963ad33cb6b85189f3385bcba46905b6d4d329db (diff) | |
Remove artificial PCI GART limitations, rename AGP to GART where
appropriate
Diffstat (limited to 'shared-core/radeon_state.c')
| -rw-r--r-- | shared-core/radeon_state.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c index baa63226..833f9698 100644 --- a/shared-core/radeon_state.c +++ b/shared-core/radeon_state.c @@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev, { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start; + int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; int numverts = (int)prim->numverts; int nbox = sarea_priv->nbox; int i = 0; @@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev, buf->idx, start, end ); if ( start != end ) { - int offset = (dev_priv->agp_buffers_offset + int offset = (dev_priv->gart_buffers_offset + buf->offset + start); int dwords = (end - start + 3) / sizeof(u32); @@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev, { drm_radeon_private_t *dev_priv = dev->dev_private; drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; - int offset = dev_priv->agp_buffers_offset + prim->offset; + int offset = dev_priv->gart_buffers_offset + prim->offset; u32 *data; int dwords; int i = 0; @@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID ); switch( param.param ) { - case RADEON_PARAM_AGP_BUFFER_OFFSET: - value = dev_priv->agp_buffers_offset; + case RADEON_PARAM_GART_BUFFER_OFFSET: + value = dev_priv->gart_buffers_offset; break; case RADEON_PARAM_LAST_FRAME: dev_priv->stats.last_frame_reads++; @@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) case RADEON_PARAM_IRQ_NR: value = dev->irq; break; - case RADEON_PARAM_AGP_BASE: - value = dev_priv->agp_vm_start; + case RADEON_PARAM_GART_BASE: + value = dev_priv->gart_vm_start; break; case RADEON_PARAM_REGISTER_HANDLE: value = dev_priv->mmio_offset; @@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS ) /* The lock is the first dword in the sarea. */ value = (int)dev->lock.hw_lock; break; - case RADEON_PARAM_AGP_TEX_HANDLE: - value = dev_priv->agp_textures_offset; + case RADEON_PARAM_GART_TEX_HANDLE: + value = dev_priv->gart_textures_offset; break; default: return DRM_ERR(EINVAL); |