diff options
| author | Dave Airlie <airlied@clockmaker.usersys.redhat.com> | 2007-11-03 00:39:44 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@clockmaker.usersys.redhat.com> | 2007-11-03 00:39:44 +1000 |
| commit | bb5f2158dbd30dbbffa3881fac75b71d71ecaaf9 (patch) | |
| tree | 3e1b2327637f73104139a072cac820c7b8ab01e2 /shared-core | |
| parent | 5766d81074d6faa7f14b45635765cdb7209597fc (diff) | |
radeon: set the address to access the aperture on the CPU side correctly
This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.
Diffstat (limited to 'shared-core')
| -rw-r--r-- | shared-core/radeon_cp.c | 5 | ||||
| -rw-r--r-- | shared-core/radeon_drv.h | 1 |
2 files changed, 4 insertions, 2 deletions
diff --git a/shared-core/radeon_cp.c b/shared-core/radeon_cp.c index 06861381..c4e13bb2 100644 --- a/shared-core/radeon_cp.c +++ b/shared-core/radeon_cp.c @@ -1694,7 +1694,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init) dev_priv->gart_info.bus_addr = dev_priv->pcigart_offset + dev_priv->fb_location; dev_priv->gart_info.mapping.offset = - dev_priv->gart_info.bus_addr; + dev_priv->pcigart_offset + dev_priv->fb_aper_offset; dev_priv->gart_info.mapping.size = dev_priv->gart_info.table_size; @@ -2295,7 +2295,8 @@ int radeon_driver_firstopen(struct drm_device *dev) if (ret != 0) return ret; - ret = drm_addmap(dev, drm_get_resource_start(dev, 0), + dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); + ret = drm_addmap(dev, dev_priv->fb_aper_offset, drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map); if (ret != 0) diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h index 006559df..e7264a88 100644 --- a/shared-core/radeon_drv.h +++ b/shared-core/radeon_drv.h @@ -301,6 +301,7 @@ typedef struct drm_radeon_private { /* starting from here on, data is preserved accross an open */ uint32_t flags; /* see radeon_chip_flags */ + unsigned long fb_aper_offset; } drm_radeon_private_t; |