diff options
| author | Eric Anholt <eric@anholt.net> | 2009-08-07 18:09:31 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-08-07 18:33:08 -0700 |
| commit | ceb8afcca5b0a52b005a782ea54b301beaee1a15 (patch) | |
| tree | 46c2b041ce77cc259f2caf7b9d925307e8d7290e /src/mesa | |
| parent | 12c6973c6e32e5ee29242cb037830c1ca081f479 (diff) | |
intel: Align region height as required for tiled regions.
Otherwise, we would address beyond the end of our buffers. Fixes reliable
GPU segfault with texture_tiling=true and oglconform shadow.c.
Bug #22406.
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_regions.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 69574f2432..497f796764 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -181,6 +181,11 @@ intel_region_alloc(struct intel_context *intel, dri_bo *buffer; struct intel_region *region; + if (tiling == I915_TILING_X) + height = ALIGN(height, 8); + else if (tiling == I915_TILING_Y) + height = ALIGN(height, 32); + if (expect_accelerated_upload) { buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region", pitch * cpp * height, 64); |