Mesa - My Mesa repository

Age	Commit message (Collapse)	Author
2008-06-21	replace __inline and __inline__ with INLINE macro	Brian Paul

2008-04-22	i965: fix DEPTH_TEXTURE_MODE (bug #14220)	Xiang, Haihao

2008-03-21	[965] Avoid emitting dead code for DPx/math instructions.	Michal Wajdeczko
	The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted.
2008-03-21	[965] Improve pinterp performance by delaying reads of just-written regs.	Michal Wajdeczko

2008-03-21	[965] Fix negating of unsigned value in emit_wpos_xy.	Michal Wajdeczko

2008-03-17	[i965] fix wpos height 1 pixel higher	Zou Nan hai

2008-03-13	[i965] multiple rendering target support	Zou Nan hai

2008-02-28	[965] Bug #9151: make fragment.position return window coords not screen coords.	Eric Anholt

2007-11-30	i965: use uncompressed instruction to ensure only	Xiang, Haihao
	Pixel Mask Copy is modified as the pixel shader thread turns off pixels based on kill instructions.
2007-10-09	shadow sampler fix.	Zou Nan hai
	1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0) 2. support shadow sampler in simd8
2007-06-21	support branch and loop in pixel shader	Zou Nan hai
	most of the sample working with some small modification
2007-04-12	Initial 965 GLSL support	Zou Nan hai

2007-02-23	Update DRI drivers for new glsl compiler.	Brian
	Mostly: - update #includes - update STATE_* token code
2006-08-09	Add Intel i965G/Q DRI driver.	Eric Anholt
	This driver comes from Tungsten Graphics, with a few further modifications by Intel.