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r600_state_predict
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The s3tc extensions are properly enabled now, when force_s3tc_enable option is set in driconf.
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Needed for occulsion queries on rv530 chips
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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r600_state_predict
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This fixes some state atom check functions from returing wrong emit size.
There is emit code cleanup so that emit function selection is done in init
time instead of runtime.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
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Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
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Supported only on HW with TCL block and with proper radeon drm.
Required minimum radeon drm version is 1.30 or KMS.
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TODO:
- use proper interface for checking if bo is idle when it's available
- disable ZTOP only when needed
- make it work under KMS
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This doesn't remove software TCL path - so RS480 and RS690 work as before.
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This almost fixes compressed mipmapped textures on r200, though some small
mip levels are still broken.
Leave r300 compressed texture stride as is though afaik it's different
to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride
at same place.
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still always enable max, but the right values this time.
More work should probably be done for saner limits without mm, and/or
dri conf option allow_large_textures (which is ignored) removed.
3D limit on r100 is pretty arbitrary as still handled by swrast anyway.
Also fix r300 limits (except 3d I've no idea what the max is anyway so
keep using mesa default).
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Conflicts:
src/mesa/drivers/dri/i915/i915_tex_layout.c
src/mesa/drivers/dri/i965/brw_wm_glsl.c
src/mesa/drivers/dri/intel/intel_buffer_objects.c
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
src/mesa/drivers/dri/intel/intel_pixel_draw.c
src/mesa/main/enums.c
src/mesa/main/texstate.c
src/mesa/vbo/vbo_exec_array.c
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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Tested with glean/texture_srgb and wine/d3d9 tests on RV535
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use the actual value set in the context
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This still need some work to actually report somethings reasonable
if no memory manager is available.
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Until now falling back to software rasterizer worked only for TCL enabled cards.
For non TCL cards we used to plug our rendering functions in r300InitSwtcl, and we had never restored original functions for software rasterizer.
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- move extensions init into seperate function
- move options handling into seperate function
- create new structure to hold options values
- use context->options.hw_tcl_enabled field instead of global hw_tcl_on and future_hw_tcl_on variables
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Fixes potential texture object leaks.
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Looks like r400 based IGP chips require 64 byte alignment
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This performance regression on non TCL hw was introduced by ed4c6cbe017b4e8bacb7e012d4baaf77a20a2c33.
This patch depends on "r300: always route 4 texcoord components to RS" and "r300: add point attenuation stage for TCL fallbacks".
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ae_create_context is called by vbo_CreateContext
ae_invalidate_state is called by vbo_InvalidateState
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- move constant values initialization to seperate function
- remove obvious comments
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Conflicts:
src/mesa/drivers/dri/r200/r200_tex.c
src/mesa/drivers/dri/r300/r300_cmdbuf.c
src/mesa/drivers/dri/r300/r300_context.h
src/mesa/drivers/dri/r300/r300_swtcl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texmem.c
src/mesa/drivers/dri/r300/r300_texstate.c
src/mesa/drivers/dri/radeon/radeon_tex.c
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Context destruction was nearly the same over all the drivers,
so collapse it down.
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Since core Mesa MAX_TEXTURE_LEVELS was bumped, we were incorrectly advertising
a maximum texture size of 4096 on older chips, causing corrupted menu text in
Extreme Tux Racer or Armagetron.
Also make sure our texture image array can actually hold all the mipmap levels
we support...
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Re work depth issues.
Do a lot more FBO abstactions
fixup depth/stencil buffer interactions
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Conflicts:
src/mesa/drivers/dri/r300/r300_cmdbuf.c
src/mesa/drivers/dri/r300/r300_state.c
src/mesa/drivers/dri/r300/r300_swtcl.c
src/mesa/drivers/dri/r300/radeon_ioctl.c
src/mesa/drivers/dri/radeon/radeon_screen.c
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Remove fixed function fog setup.
Signed-off-by: Nicolai Haehnle <nhaehnle@gmail.com>
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this is a step towards fbos and should fix pageflipping, but
I think the first flip seems broken.
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Flush the VAP the first time for each state atom we upload new
VAP data
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Conflicts:
configure.ac
src/mesa/drivers/dri/r200/r200_context.c
src/mesa/drivers/dri/r300/r300_render.c
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