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path: root/src/mesa/drivers/dri/radeon
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2009-06-20radeon: make cubemap mipmap generation workRoland Scheidegger
need to pass target parameter to radeon_teximage/radeon_subteximage functions otherwise mipmap generation for cube maps can't work (assert/segfault in _mesa_generate_mipmap)
2009-06-19radeon: fix cube maps for non-mm pathRoland Scheidegger
drm cmd checker would refuse cube emits also fix an issue in the cs path which would calculate the register offset off by one dword. Only same testing done as original code (none except compile tested).
2009-06-19radeons: use dp4 for position invariant vertex programsRoland Scheidegger
Fixes #22181. R200 requires this since DP4 is used in hw tnl mode. R300 prefers it (should be faster due to no instruction dependencies), but both methods should be correct (when sw tcl is used though, MUL/MAD might be faster). Probably doesn't make much difference for R100 since vertex progs are executed in software anyway, but let's just keep it the same there too.
2009-06-18radeon: don't re-add BOs to validate listDave Airlie
if its on the list its on the list don't go readding it. multitexturing from the same texture could cause this.
2009-06-17radeon: Flush command buffer on viewport changeJerome Glisse
We flush the command buffer so we don't emit mixed state (with new and previous buffer size) command buffer, this is especialy affecting zbuffer states.
2009-06-17radeon: fix warnings in wrapper with libdrmDave Airlie
2009-06-15r300: fix 3D texturesMaciej Cencora
2009-06-12r300: add support for EXT_texture_sRGBMaciej Cencora
Tested with glean/texture_srgb and wine/d3d9 tests on RV535
2009-06-12radeon: fix size of mipmap texture arrayDave Airlie
2009-06-12radeon/r200/r300: fix max texture levels assertDave Airlie
use the actual value set in the context
2009-06-11radeon: increase max bo countMaciej Cencora
2009-06-09radeon: fix mipmap_limits crasher.Dave Airlie
This gets the correct srclvl image map when uploading images to the new mipmap.
2009-06-01radeon: Provide a more detailled GL_RENDERER string.Nicolai Hähnle
Display the chip family and PCI ID. This can be parsed easily, and essentially all information that the driver has about the chip can be deduced from it. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-05-27radeon: emit scissor before emiting verticesJerome Glisse
2009-05-27radeon: emit scissor when using cs submission style.Jerome Glisse
2009-05-25radeon: on update drawable don't firevertices as it might be call from GetLockJerome Glisse
To avoid locking bug we shouldn't not call firevertices from this path as it's call from radeon get lock.
2009-05-24radeon: realloc dma if needed after revalidateJerome Glisse
Revalidate can trigger flushing and dma buffer deallocation, so retry allocation on such case.
2009-05-24radeon: Remove drawable & readable from radeon_dri_mirrorNicolai Hähnle
The duplication of state data caused a crash due to double-free on destruction of context, because a variable wasn't correctly null'ed out. Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-05-22radeon: reading back to scratch reg through status map doesn't workJerome Glisse
For some unknown reasons the scratch reg value doesn't endup in the status map at the scratch reg offset, this is a temporary work around until we figure out why it doesn't work.
2009-05-21radeon: maxbuffer size is in bytesJerome Glisse
2009-05-20r200: fix vbo array renderingJerome Glisse
2009-05-20radeon: Increase reference count of current renderbuffers.Michel Dänzer
Fixes glxinfo: main/renderbuffer.c:2159: _mesa_reference_renderbuffer: Assertion `oldRb->Magic == 0xaabbccdd' failed.
2009-05-20radeon: set max texture sizeJerome Glisse
This still need some work to actually report somethings reasonable if no memory manager is available.
2009-05-13R1xx/r2xx: Don't use an alpha texture format for GLX_TEXTURE_FORMAT_RGB_EXTAlex Deucher
In r*00SetTexBuffer2(), if the passed in text glx_texture_format is GLX_TEXTURE_FORMAT_RGB_EXT, then we should use an RGB-only texture format, even if the DRI buffer has four channels. https://bugs.freedesktop.org/show_bug.cgi?id=21609
2009-05-13radeon: Don't crash generating mipmaps when pixels=NULLOwen W. Taylor
When a NULL value of pixels is passed to TexImage2D and SGIS_generate_mipmap is enabled, don't try to generate the mipmap tree: we don't have data yet for the texture and will crash. https://bugs.freedesktop.org/show_bug.cgi?id=21648
2009-05-13Call _mesa_update_stencil() before accessing ctx->Stencil._EnabledOwen W. Taylor
ctx->Stencil._Enabled is derived state and not immediately updated when the stencil parameters are changed; we need to make sure that it is up-to-date before accessing it. https://bugs.freedesktop.org/show_bug.cgi?id=21608
2009-05-12radeon: glReadBuffer set _NEW_BUFFERS, not _NEW_PIXELJerome Glisse
This was broken with last merge see 62043b27575c378c027251316421e4699f461108 for explanations
2009-05-12radeon: avoid segfault in radeon_update_renderbuffers() if using DRI1Tormod Volden
Basically the same as 43d9020ff1e975e7f4f9480d9ef24f0b9fb2141f for intel. Bug 21688. Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
2009-05-10radeon: add support for new dri2 interfaces & fix single buffer renderingJoel Bosveld
2009-05-09radeon: don't include cs uncondionalyJerome Glisse
2009-05-08radeon: IRQ always enabled in DRI2 path no need to query kernel for itJerome Glisse
2009-05-07r300: fix compiler warningsMaciej Cencora
2009-05-06When clearing the stencil buffer, don't use a two-sided stencilOwen W. Taylor
In radeon_clear_tris(), when clearing the stencil buffer, pass GL_FRONT_AND_BACK to _mesa_StencilFuncSeparate(), to avoid triggering a software fallback on r300 and below. https://bugs.freedesktop.org/show_bug.cgi?id=21601
2009-05-06radeon: hopefully fixup radeon cube state emission for kmsDave Airlie
2009-05-06r100/r200: try and allocate miptree correct for hw.Dave Airlie
This doesn't make things worse but according to sroland it is how the GPU hw expects things on the r100/r200
2009-05-05radeon/r200: enable all the optional drm support bitsDave Airlie
2009-05-04r300: set proper texture row alignment for IGP chipsMaciej Cencora
Looks like r400 based IGP chips require 64 byte alignment
2009-04-28R300: add quadpipe overridesAlex Deucher
RV410 SE chips only have 1 quadpipe. Also, handle other R300 chip with quadpipe override.
2009-04-28radeno: cleanup the startup path furtherDave Airlie
2009-04-28radeon: further cleanup dri1 screen initDave Airlie
2009-04-28radeon: remove kernel mm, dri2 path takes care of itDave Airlie
2009-04-27r300: fix valgrind warningsMaciej Cencora
2009-04-27r300: add atom print function for kernel mm pathMaciej Cencora
2009-04-19r300: revert part of cb4bef7ae0b5fe8de82c380bc98f19067394d355Maciej Cencora
Some debugging code got there by accident
2009-04-19r300: general cleanupMaciej Cencora
- remove unused fields - remove unused defines and macros - flatten one structure
2009-04-19radeon: update clear state with latest intel codeDave Airlie
2009-04-16radeon: take a bo reference when adding to validate listDave Airlie
2009-04-12radeon: emit scissor when using cs pathJerome Glisse
2009-04-09Merge remote branch 'origin/master' into radeon-rewriteDave Airlie
Conflicts: src/mesa/drivers/dri/r200/r200_tex.c src/mesa/drivers/dri/r300/r300_cmdbuf.c src/mesa/drivers/dri/r300/r300_context.h src/mesa/drivers/dri/r300/r300_swtcl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texmem.c src/mesa/drivers/dri/r300/r300_texstate.c src/mesa/drivers/dri/radeon/radeon_tex.c
2009-04-07radeon: fix compiler warningAlex Deucher
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