Age | Commit message (Collapse) | Author | |
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2009-11-19 | Merge branch 'master' of ssh://richardradeon@git.freedesktop.org/git/mesa/mesa | Richard Li | |
2009-11-19 | r600 : check in shader code test enable flag: if flag | Richard Li | |
R600_ENABLE_GLSL_TEST defined, IL shader code will goto r600 assembler. The test base is /mesa/progs/glsl/brick, and changes shader code in CH06-brick.frag/vert to test different logic op combination. (if,else,while,function,...). The stack depth code is not in yet, so it is hard coded now. So complex code would not run (such as things like 8 loops embeded loop in loop). | |||
2009-11-19 | intel: Remove non-GEM support. | Eric Anholt | |
This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked. | |||
2009-11-19 | intel: Remove dead intel_context members and move some packing around. | Eric Anholt | |
2009-11-19 | intel: Remove our special color packing macros and just use colormac.h. | Eric Anholt | |
2009-11-19 | intel: Pack colors for blit at blit time, rather than at ClearColor. | Eric Anholt | |
2009-11-19 | intel: Consistently use no_batch_wrap in intel_context struct. | Eric Anholt | |
2009-11-19 | i965: Pack brw_wm_fragment_program better. | Eric Anholt | |
2009-11-19 | mesa: Remove gratuitous padding in prog_dst_register. | Eric Anholt | |
The padding was there to indicate the amount of space left from the number of expected bytes in the struct minus allocated bits. But uint bitfields get packed so that they don't cross uint boundaries, and we ended up allocating an extra dword to hold the pad field! | |||
2009-11-19 | i965: Pack the brw_wm_prog_key better. | Eric Anholt | |
2009-11-19 | i915: Remove dead meta_draw_quad code. | Eric Anholt | |
2009-11-19 | tnl: Replace deprecated FogCoordPtr with AttribPtr[_TNL_ATTRIB_FOG] | Eric Anholt | |
2009-11-19 | tnl: Replace deprecated ColorPtr[] with AttribPtr or new BackfaceColorPtr. | Eric Anholt | |
2009-11-19 | tnl: Replace deprecated ObjPtr with AttribPtr[_TNL_ATTRIB_POS] | Eric Anholt | |
2009-11-19 | tnl: Replace deprecated TexCoordPtr with AttribPtr[_TNL_ATTRIB_TEX*] | Eric Anholt | |
2009-11-19 | tnl: Replace NormalPtr with AttribPtr[_TNL_ATTRIB_NORMAL] | Eric Anholt | |
2009-11-18 | r600 : update PS and VS emit count for loop constants. | Richard Li | |
2009-11-18 | r600 : add some defs | Richard Li | |
2009-11-18 | r600 : Initial version of glsl fc. | Richard Li | |
2009-11-17 | Merge branch 'outputswritten64' | Ian Romanick | |
Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h | |||
2009-11-17 | r300: fix reads and writes for MESA_FORMAT_S8Z24 buffer | Maciej Cencora | |
Regression was introduced by texformat-rework branch merge. | |||
2009-11-17 | Remove unconditional use of glibc specific bswap_16() macro. | Michel Dänzer | |
Fixes unresolved symbol bswap_16 on non-glibc or little endian glibc platforms. | |||
2009-11-17 | dri: Ensure subdirs have finished before linking driver | Dan Nicholson | |
Recursive make is hard. If there are subdirectories in the DRI drivers, it's pretty certain we want to finish building in them before linking the driver. Add a new target to serialize the rules. Signed-off-by: Dan Nicholson <dbn.lists@gmail.com> | |||
2009-11-17 | r600: More span breakage fixes. | Michel Dänzer | |
At least now the compiler doesn't complain about implicitly declared functions anymore... | |||
2009-11-17 | r600: Attempt to fix span breakage introduced by big endian fixes. | Michel Dänzer | |
Only compile tested; I happened to notice people on IRC reporting .../r600_dri.so: undefined symbol: radeon_ptr_2byte_8x2 | |||
2009-11-17 | radeon: Depth/stencil span code fixes for big endian. | Michel Dänzer | |
Fixes e.g. text in progs/demos/arbocclude. | |||
2009-11-17 | radeon: Fix occlusion queries on big endian. | Michel Dänzer | |
2009-11-17 | radeon: Fix software fallbacks with KMS on big endian. | Michel Dänzer | |
2009-11-17 | radeon: FBO fixes for big endian. | Michel Dänzer | |
2009-11-17 | radeon: rn50's have no 3D engine so don't try and init 3D driver. | Dave Airlie | |
2009-11-16 | i965: Use MESA_FORMAT_AL1616 when appropriate | Ian Romanick | |
2009-11-16 | r600: don't force Z order | Alex Deucher | |
Let the hw decide (early vs late Z) fixes fdo bug 25092 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> | |||
2009-11-16 | mesa: remove unused vertex array driver hooks | Brian Paul | |
2009-11-13 | i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.c | Eric Anholt | |
This should fix TXB on G45 and older in the GLSL case. | |||
2009-11-13 | i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c. | Eric Anholt | |
New comments should explain some of the confusion about how this message works. | |||
2009-11-13 | i965: Clean up emit_tex a bit. | Eric Anholt | |
2009-11-13 | Merge remote branch 'origin/mesa_7_6_branch' | Eric Anholt | |
2009-11-13 | i965: Flag BRW_NEW_CONTEXT on some context state. | Eric Anholt | |
Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965). | |||
2009-11-13 | intel: Remove some dead context structure fields. | Eric Anholt | |
2009-11-13 | i965: Remove an unused cache_item field. | Eric Anholt | |
2009-11-13 | i965: Remove long dead structures for ffvertex_prog.c. | Eric Anholt | |
2009-11-13 | i965: Use bo_map instead of subdata to upload the bits of constant buffer. | Eric Anholt | |
Saves CPU time, resulting in a 2.5% FPS win on ETQW. | |||
2009-11-13 | i965: Validate the number of URB entries selected for the VS. | Eric Anholt | |
2009-11-13 | intel: When subdataing a busy buffer, use a temporary and blit in. | Eric Anholt | |
This cuts a massive number of waits in ET:QW, which uses a VBO ringbuffer. Unfortunately it doesn't BufferData when wrapping back to 0, so we can't be clever with tracking what's been initialized. | |||
2009-11-13 | i965: Clean up Ironlake sampler type definitions. | Eric Anholt | |
They're the same regardless of execution width for 8, 4x2, and 16. | |||
2009-11-13 | i965: Avoid moving the current value back into the accumulator for MAD. | Eric Anholt | |
This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms. | |||
2009-11-12 | intel: Don't check for context pointer to be NULL during extension init | Ian Romanick | |
Thanks to Chia-I Wu's changes to the extension function infrastructure, we no longer have to tell the loader which extensions the driver might enable. This means that intelInitExtensions will never be called with a NULL context pointer. Remove all the NULL checks. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> | |||
2009-11-12 | intel: Remove unused enable_imaging parameter to intelInitExtensions | Ian Romanick | |
2009-11-12 | i965: Fix Ironlake shadow comparisons. | Eric Anholt | |
The cube map array index arg is always present. | |||
2009-11-12 | i965: Fix VBO last-valid-offset setup on Ironlake. | Eric Anholt | |
Instead of doing math based on the (broken for VBO && offset != 0) input->count number, just use the BO size. Fixes assertion failure in ETQW. |