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-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/cpufreq.c287
-rw-r--r--arch/arm/mach-imx/generic.c9
-rw-r--r--arch/arm/mach-imx/irq.c14
-rw-r--r--arch/arm/mach-imx/time.c86
5 files changed, 354 insertions, 44 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 0b27d79f2ef..02272aa36e9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,6 +9,8 @@
obj-y += irq.o time.o dma.o generic.o
+obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
+
# Specific board support
obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
new file mode 100644
index 00000000000..ac5f9989566
--- /dev/null
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -0,0 +1,287 @@
+/*
+ * cpu.c: clock scaling for the iMX
+ *
+ * Copyright (C) 2000 2001, The Delft University of Technology
+ * Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
+ * Copyright (C) 2006 Inky Lung <ilung@cwlinux.com>
+ * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
+ *
+ * Based on SA1100 version written by:
+ * - Johan Pouwelse (J.A.Pouwelse@its.tudelft.nl): initial version
+ * - Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+/*#define DEBUG*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/cpufreq.h>
+#include <asm/system.h>
+
+#include <asm/hardware.h>
+
+#include "generic.h"
+
+#ifndef __val2mfld
+#define __val2mfld(mask,val) (((mask)&~((mask)<<1))*(val)&(mask))
+#endif
+#ifndef __mfld2val
+#define __mfld2val(mask,val) (((val)&(mask))/((mask)&~((mask)<<1)))
+#endif
+
+#define CR_920T_CLOCK_MODE 0xC0000000
+#define CR_920T_FASTBUS_MODE 0x00000000
+#define CR_920T_ASYNC_MODE 0xC0000000
+
+static u32 mpctl0_at_boot;
+
+static void imx_set_async_mode(void)
+{
+ adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
+}
+
+static void imx_set_fastbus_mode(void)
+{
+ adjust_cr(CR_920T_CLOCK_MODE, CR_920T_FASTBUS_MODE);
+}
+
+static void imx_set_mpctl0(u32 mpctl0)
+{
+ unsigned long flags;
+
+ if (mpctl0 == 0) {
+ local_irq_save(flags);
+ CSCR &= ~CSCR_MPEN;
+ local_irq_restore(flags);
+ return;
+ }
+
+ local_irq_save(flags);
+ MPCTL0 = mpctl0;
+ CSCR |= CSCR_MPEN;
+ local_irq_restore(flags);
+}
+
+/**
+ * imx_compute_mpctl - compute new PLL parameters
+ * @new_mpctl: pointer to location assigned by new PLL control register value
+ * @cur_mpctl: current PLL control register parameters
+ * @freq: required frequency in Hz
+ * @relation: is one of %CPUFREQ_RELATION_L (supremum)
+ * and %CPUFREQ_RELATION_H (infimum)
+ */
+long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation)
+{
+ u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
+ u32 mfi;
+ u32 mfn;
+ u32 mfd;
+ u32 pd;
+ unsigned long long ll;
+ long l;
+ long quot;
+
+ /* Fdppl=2*Fref*(MFI+MFN/(MFD+1))/(PD+1) */
+ /* PD=<0,15>, MFD=<1,1023>, MFI=<5,15> MFN=<0,1022> */
+
+ if (cur_mpctl) {
+ mfd = ((cur_mpctl >> 16) & 0x3ff) + 1;
+ pd = ((cur_mpctl >> 26) & 0xf) + 1;
+ } else {
+ pd=2; mfd=313;
+ }
+
+ /* pd=2; mfd=313; mfi=8; mfn=183; */
+ /* (MFI+MFN/(MFD)) = Fdppl / (2*Fref) * (PD); */
+
+ quot = (f_ref + (1 << 9)) >> 10;
+ l = (freq * pd + quot) / (2 * quot);
+ mfi = l >> 10;
+ mfn = ((l & ((1 << 10) - 1)) * mfd + (1 << 9)) >> 10;
+
+ mfd -= 1;
+ pd -= 1;
+
+ *new_mpctl = ((mfi & 0xf) << 10) | (mfn & 0x3ff) | ((mfd & 0x3ff) << 16)
+ | ((pd & 0xf) << 26);
+
+ ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
+ quot = (pd+1) * (1<<16);
+ ll += quot / 2;
+ do_div(ll, quot);
+ freq = ll;
+
+ pr_debug(KERN_DEBUG "imx: new PLL parameters pd=%d mfd=%d mfi=%d mfn=%d, freq=%ld\n",
+ pd, mfd, mfi, mfn, freq);
+
+ return freq;
+}
+
+
+static int imx_verify_speed(struct cpufreq_policy *policy)
+{
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
+
+ return 0;
+}
+
+static unsigned int imx_get_speed(unsigned int cpu)
+{
+ unsigned int freq;
+ unsigned int cr;
+ unsigned int cscr;
+ unsigned int bclk_div;
+
+ if (cpu)
+ return 0;
+
+ cscr = CSCR;
+ bclk_div = __mfld2val(CSCR_BCLK_DIV, cscr) + 1;
+ cr = get_cr();
+
+ if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
+ freq = imx_get_system_clk();
+ freq = (freq + bclk_div/2) / bclk_div;
+ } else {
+ freq = imx_get_mcu_clk();
+ if (cscr & CSCR_MPU_PRESC)
+ freq /= 2;
+ }
+
+ freq = (freq + 500) / 1000;
+
+ return freq;
+}
+
+static int imx_set_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ u32 mpctl0 = 0;
+ u32 cscr;
+ unsigned long flags;
+ long freq;
+ long sysclk;
+ unsigned int bclk_div = 1;
+
+ freq = target_freq * 1000;
+
+ pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
+ freq, mpctl0_at_boot);
+
+ sysclk = imx_get_system_clk();
+
+ if (freq > sysclk + 1000000) {
+ freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation);
+ if (freq < 0) {
+ printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq);
+ return -EINVAL;
+ }
+ } else {
+ if(freq + 1000 < sysclk) {
+ if (relation == CPUFREQ_RELATION_L)
+ bclk_div = (sysclk - 1000) / freq;
+ else
+ bclk_div = (sysclk + freq + 1000) / freq;
+
+ if(bclk_div > 16)
+ bclk_div = 16;
+ }
+ freq = (sysclk + bclk_div / 2) / bclk_div;
+ }
+
+ freqs.old = imx_get_speed(0);
+ freqs.new = (freq + 500) / 1000;
+ freqs.cpu = 0;
+ freqs.flags = 0;
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ local_irq_save(flags);
+
+ imx_set_fastbus_mode();
+
+ imx_set_mpctl0(mpctl0);
+
+ cscr = CSCR;
+ cscr &= ~CSCR_BCLK_DIV;
+ cscr |= __val2mfld(CSCR_BCLK_DIV, bclk_div - 1);
+ CSCR = cscr;
+
+ if(mpctl0) {
+ CSCR |= CSCR_MPLL_RESTART;
+
+ /* Wait until MPLL is stablized */
+ while( CSCR & CSCR_MPLL_RESTART );
+
+ imx_set_async_mode();
+ }
+
+ local_irq_restore(flags);
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ pr_debug(KERN_INFO "imx: set frequency %ld Hz, running from %s\n",
+ freq, mpctl0? "MPLL": "SPLL");
+
+ return 0;
+}
+
+static int __init imx_cpufreq_driver_init(struct cpufreq_policy *policy)
+{
+ printk(KERN_INFO "i.MX cpu freq change driver v1.0\n");
+
+ if (policy->cpu != 0)
+ return -EINVAL;
+
+ policy->cur = policy->min = policy->max = imx_get_speed(0);
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+ policy->cpuinfo.min_freq = 8000;
+ policy->cpuinfo.max_freq = 200000;
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+ return 0;
+}
+
+static struct cpufreq_driver imx_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = imx_verify_speed,
+ .target = imx_set_target,
+ .get = imx_get_speed,
+ .init = imx_cpufreq_driver_init,
+ .name = "imx",
+};
+
+static int __init imx_cpufreq_init(void)
+{
+
+ mpctl0_at_boot = 0;
+
+ if((CSCR & CSCR_MPEN) &&
+ ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
+ mpctl0_at_boot = MPCTL0;
+
+ return cpufreq_register_driver(&imx_driver);
+}
+
+arch_initcall(imx_cpufreq_init);
+
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 12ea58a3b84..b5aa49d00ca 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -104,6 +104,9 @@ EXPORT_SYMBOL(imx_gpio_mode);
*/
static unsigned int imx_decode_pll(unsigned int pll)
{
+ unsigned long long ll;
+ unsigned long quot;
+
u32 mfi = (pll >> 10) & 0xf;
u32 mfn = pll & 0x3ff;
u32 mfd = (pll >> 16) & 0x3ff;
@@ -112,7 +115,11 @@ static unsigned int imx_decode_pll(unsigned int pll)
mfi = mfi <= 5 ? 5 : mfi;
- return (2 * (f_ref>>10) * ( (mfi<<10) + (mfn<<10) / (mfd+1) )) / (pd+1);
+ ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
+ quot = (pd+1) * (1<<16);
+ ll += quot / 2;
+ do_div(ll, quot);
+ return (unsigned int) ll;
}
unsigned int imx_get_system_clk(void)
diff --git a/arch/arm/mach-imx/irq.c b/arch/arm/mach-imx/irq.c
index 368b13b058a..0791b56caec 100644
--- a/arch/arm/mach-imx/irq.c
+++ b/arch/arm/mach-imx/irq.c
@@ -146,7 +146,7 @@ imx_gpio_unmask_irq(unsigned int irq)
static void
imx_gpio_handler(unsigned int mask, unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
desc = irq_desc + irq;
while (mask) {
@@ -161,7 +161,7 @@ imx_gpio_handler(unsigned int mask, unsigned int irq,
}
static void
-imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@@ -171,7 +171,7 @@ imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
-imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@@ -181,7 +181,7 @@ imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
-imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@@ -191,7 +191,7 @@ imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
}
static void
-imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc)
+imx_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
{
unsigned int mask, irq;
@@ -230,13 +230,13 @@ imx_init_irq(void)
for (irq = 0; irq < IMX_IRQS; irq++) {
set_irq_chip(irq, &imx_internal_chip);
- set_irq_handler(irq, do_level_IRQ);
+ set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
set_irq_chip(irq, &imx_gpio_chip);
- set_irq_handler(irq, do_edge_IRQ);
+ set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID);
}
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 8ae4a2c5066..40039b2a90b 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -14,6 +14,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/time.h>
+#include <linux/clocksource.h>
#include <asm/hardware.h>
#include <asm/io.h>
@@ -24,33 +25,7 @@
/* Use timer 1 as system timer */
#define TIMER_BASE IMX_TIM1_BASE
-/*
- * Returns number of us since last clock interrupt. Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long imx_gettimeoffset(void)
-{
- unsigned long ticks;
-
- /*
- * Get the current number of ticks. Note that there is a race
- * condition between us reading the timer and checking for
- * an interrupt. We get around this by ensuring that the
- * counter has not reloaded between our two reads.
- */
- ticks = IMX_TCN(TIMER_BASE);
-
- /*
- * Interrupt pending? If so, we've reloaded once already.
- */
- if (IMX_TSTAT(TIMER_BASE) & TSTAT_COMP)
- ticks += LATCH;
-
- /*
- * Convert the ticks to usecs
- */
- return (1000000 / CLK32) * ticks;
-}
+static unsigned long evt_diff;
/*
* IRQ handler for the timer
@@ -58,14 +33,23 @@ static unsigned long imx_gettimeoffset(void)
static irqreturn_t
imx_timer_interrupt(int irq, void *dev_id)
{
- write_seqlock(&xtime_lock);
+ uint32_t tstat;
/* clear the interrupt */
- if (IMX_TSTAT(TIMER_BASE))
- IMX_TSTAT(TIMER_BASE) = 0;
+ tstat = IMX_TSTAT(TIMER_BASE);
+ IMX_TSTAT(TIMER_BASE) = 0;
+
+ if (tstat & TSTAT_COMP) {
+ do {
+
+ write_seqlock(&xtime_lock);
+ timer_tick();
+ write_sequnlock(&xtime_lock);
+ IMX_TCMP(TIMER_BASE) += evt_diff;
- timer_tick();
- write_sequnlock(&xtime_lock);
+ } while (unlikely((int32_t)(IMX_TCMP(TIMER_BASE)
+ - IMX_TCN(TIMER_BASE)) < 0));
+ }
return IRQ_HANDLED;
}
@@ -77,9 +61,9 @@ static struct irqaction imx_timer_irq = {
};
/*
- * Set up timer interrupt, and return the current time in seconds.
+ * Set up timer hardware into expected mode and state.
*/
-static void __init imx_timer_init(void)
+static void __init imx_timer_hardware_init(void)
{
/*
* Initialise to a known state (all timers off, and timing reset)
@@ -87,7 +71,38 @@ static void __init imx_timer_init(void)
IMX_TCTL(TIMER_BASE) = 0;
IMX_TPRER(TIMER_BASE) = 0;
IMX_TCMP(TIMER_BASE) = LATCH - 1;
- IMX_TCTL(TIMER_BASE) = TCTL_CLK_32 | TCTL_IRQEN | TCTL_TEN;
+
+ IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_IRQEN | TCTL_TEN;
+ evt_diff = LATCH;
+}
+
+cycle_t imx_get_cycles(void)
+{
+ return IMX_TCN(TIMER_BASE);
+}
+
+static struct clocksource clocksource_imx = {
+ .name = "imx_timer1",
+ .rating = 200,
+ .read = imx_get_cycles,
+ .mask = 0xFFFFFFFF,
+ .shift = 20,
+ .is_continuous = 1,
+};
+
+static int __init imx_clocksource_init(void)
+{
+ clocksource_imx.mult =
+ clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift);
+ clocksource_register(&clocksource_imx);
+
+ return 0;
+}
+
+static void __init imx_timer_init(void)
+{
+ imx_timer_hardware_init();
+ imx_clocksource_init();
/*
* Make irqs happen for the system timer
@@ -97,5 +112,4 @@ static void __init imx_timer_init(void)
struct sys_timer imx_timer = {
.init = imx_timer_init,
- .offset = imx_gettimeoffset,
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 03:44:27 +0000