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authorEric Anholt <eric@anholt.net>2008-07-26 17:12:04 -0700
committerEric Anholt <eric@anholt.net>2008-07-26 17:39:23 -0700
commit902e401a384a8213d1239aae42bc2b7071ad6bd8 (patch)
tree9d43e9f653e4f6e6927b618329b473fef038954f
parent1e645b365900cf1c71ca5594bd6b549a1f203040 (diff)
intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.
Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't actually been tested.
-rw-r--r--src/mesa/drivers/dri/intel/intel_fbo.c8
-rw-r--r--src/mesa/drivers/dri/intel/intel_span.c64
2 files changed, 72 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 254f3efae0..5bd2ebfdcf 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -212,6 +212,14 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb,
case GL_RGB10:
case GL_RGB12:
case GL_RGB16:
+ rb->_ActualFormat = GL_RGB8;
+ rb->DataType = GL_UNSIGNED_BYTE;
+ rb->RedBits = 8;
+ rb->GreenBits = 8;
+ rb->BlueBits = 8;
+ rb->AlphaBits = 0;
+ cpp = 4;
+ break;
case GL_RGBA:
case GL_RGBA2:
case GL_RGBA4:
diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c
index 06f7c9b4b7..079b9e6a9d 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -74,6 +74,15 @@ pread_32(struct intel_renderbuffer *irb, uint32_t offset)
return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1)));
}
+static uint32_t
+pread_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset)
+{
+ get_span_cache(irb, offset);
+
+ return *(uint32_t *)(irb->span_cache + (offset & (SPAN_CACHE_SIZE - 1))) |
+ 0xff000000;
+}
+
static uint16_t
pread_16(struct intel_renderbuffer *irb, uint32_t offset)
{
@@ -99,6 +108,14 @@ pwrite_32(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
}
static void
+pwrite_xrgb8888(struct intel_renderbuffer *irb, uint32_t offset, uint32_t val)
+{
+ clear_span_cache(irb);
+
+ dri_bo_subdata(irb->region->buffer, offset, 3, &val);
+}
+
+static void
pwrite_16(struct intel_renderbuffer *irb, uint32_t offset, uint16_t val)
{
clear_span_cache(irb);
@@ -301,6 +318,17 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define PUT_VALUE(X, Y, V) pwrite_32(irb, no_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
+/* 32 bit, xRGB8888 color spanline and pixel functions
+ */
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel##x##_xRGB8888
+#define TAG2(x,y) intel##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, no_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
/* 16 bit RGB565 color tile spanline and pixel functions
*/
@@ -343,6 +371,27 @@ static uint32_t y_tile_swizzle(struct intel_renderbuffer *irb,
#define PUT_VALUE(X, Y, V) pwrite_32(irb, y_tile_swizzle(irb, intel, X, Y), V)
#include "spantmp2.h"
+/* 32 bit xRGB888 color tile spanline and pixel functions
+ */
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_XTile_##x##_xRGB8888
+#define TAG2(x,y) intel_XTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, x_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
+#define SPANTMP_PIXEL_FMT GL_BGRA
+#define SPANTMP_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
+
+#define TAG(x) intel_YTile_##x##_xRGB8888
+#define TAG2(x,y) intel_YTile_##x##_xRGB8888##y
+#define GET_VALUE(X, Y) pread_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y))
+#define PUT_VALUE(X, Y, V) pwrite_xrgb8888(irb, y_tile_swizzle(irb, intel, X, Y), V)
+#include "spantmp2.h"
+
#define LOCAL_DEPTH_VARS \
struct intel_context *intel = intel_context(ctx); \
struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
@@ -677,6 +726,21 @@ intel_set_span_functions(struct intel_context *intel,
break;
}
}
+ else if (rb->_ActualFormat == GL_RGB8) {
+ /* 8888 RGBx */
+ switch (tiling) {
+ case I915_TILING_NONE:
+ default:
+ intelInitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_X:
+ intel_XTile_InitPointers_xRGB8888(rb);
+ break;
+ case I915_TILING_Y:
+ intel_YTile_InitPointers_xRGB8888(rb);
+ break;
+ }
+ }
else if (rb->_ActualFormat == GL_RGBA8) {
/* 8888 RGBA */
switch (tiling) {