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authorEric Anholt <eric@anholt.net>2009-06-09 16:12:43 -0700
committerEric Anholt <eric@anholt.net>2009-06-09 16:12:43 -0700
commitb30dc2c66aeaad6661eef515a08a3da89aa07cb2 (patch)
treedf79cf877c4c707967b8d4acc163a8d1205ee9d3
parent38eddf04ed04966db09b67de4cdabef681dc2696 (diff)
i915: Add an option for testing the effect of early Z in classic mode.
The early Z stuff is supposed to be unsafe without some more work in the enable/disable path (in particular, how do we want to get it disabled on the way out to the X Server?), but at the moment is 6% in OA.
-rw-r--r--src/mesa/drivers/dri/i915/i915_reg.h1
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c9
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c1
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h1
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c6
5 files changed, 17 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h
index b02e2c7628..84db58ea95 100644
--- a/src/mesa/drivers/dri/i915/i915_reg.h
+++ b/src/mesa/drivers/dri/i915/i915_reg.h
@@ -141,6 +141,7 @@
/* p161 */
#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16))
/* Dword 1 */
+#define CLASSIC_EARLY_DEPTH (1<<31)
#define TEX_DEFAULT_COLOR_OGL (0<<30)
#define TEX_DEFAULT_COLOR_D3D (1<<30)
#define ZR_EARLY_DEPTH (1<<29)
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 6ecbc4709b..2fca247af1 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -42,6 +42,7 @@
#include "intel_regions.h"
#include "intel_tris.h"
#include "intel_fbo.h"
+#include "intel_chipset.h"
#include "i915_reg.h"
#include "i915_context.h"
@@ -611,6 +612,14 @@ i915_state_draw_region(struct intel_context *intel,
}
}
+ /* This isn't quite safe, thus being hidden behind an option. When changing
+ * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
+ * can only be set when a depth buffer is already defined.
+ */
+ if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
+ depth_region->tiling != I915_TILING_NONE)
+ value |= CLASSIC_EARLY_DEPTH;
+
if (depth_region && depth_region->cpp == 4) {
value |= DEPTH_FRMT_24_FIXED_8_OTHER;
}
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 3a94843993..f88b37d0f3 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -729,6 +729,7 @@ intelInitContext(struct intel_context *intel,
}
intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
"texture_tiling");
+ intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
intel->prim.primitive = ~0;
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 4e45f1a91f..7d3c80bb21 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -306,6 +306,7 @@ struct intel_context
GLboolean is_front_buffer_rendering;
GLboolean use_texture_tiling;
+ GLboolean use_early_z;
drm_clip_rect_t fboRect; /**< cliprect for FBO rendering */
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 53782c5604..8da96ede64 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -75,6 +75,10 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_TEXTURE_TILING(true)
#endif
+ DRI_CONF_OPT_BEGIN(early_z, bool, false)
+ DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).")
+ DRI_CONF_OPT_END
+
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_FORCE_S3TC_ENABLE(false)
@@ -87,7 +91,7 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_END
DRI_CONF_END;
-const GLuint __driNConfigOptions = 9;
+const GLuint __driNConfigOptions = 10;
#ifdef USE_NEW_INTERFACE
static PFNGLXCREATECONTEXTMODES create_context_modes = NULL;