diff options
| author | Ian Romanick <idr@us.ibm.com> | 2008-03-17 15:45:52 -0700 |
|---|---|---|
| committer | Ian Romanick <idr@us.ibm.com> | 2008-03-17 15:47:45 -0700 |
| commit | 1936e4bdfd776f78f9fe44f77ce66066fd166360 (patch) | |
| tree | c72c00d624d332733d2b643e3dffd5114b18cc34 /src/gallium/drivers/cell/spu/spu_render.c | |
| parent | 0c715de39fa8337a2753dacd77ed280000416c1a (diff) | |
cell: Initial code-gen for alpha / stencil / depth testing
Alpha test is currently broken because all per-fragment testing occurs
before alpha is calculated.
Stencil test is currently broken because the Z-clear code asserts if
there is a stencil buffer.
Diffstat (limited to 'src/gallium/drivers/cell/spu/spu_render.c')
| -rw-r--r-- | src/gallium/drivers/cell/spu/spu_render.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/cell/spu/spu_render.c b/src/gallium/drivers/cell/spu/spu_render.c index 20e77aa2e6..6df59abd36 100644 --- a/src/gallium/drivers/cell/spu/spu_render.c +++ b/src/gallium/drivers/cell/spu/spu_render.c @@ -98,7 +98,7 @@ my_tile(uint tx, uint ty) static INLINE void get_cz_tiles(uint tx, uint ty) { - if (spu.depth_stencil.depth.enabled) { + if (spu.read_depth) { if (spu.cur_ztile_status != TILE_STATUS_CLEAR) { //printf("SPU %u: getting Z tile %u, %u\n", spu.init.id, tx, ty); get_tile(tx, ty, &spu.ztile, TAG_READ_TILE_Z, 1); @@ -153,7 +153,7 @@ static INLINE void wait_put_cz_tiles(void) { wait_on_mask(1 << TAG_WRITE_TILE_COLOR); - if (spu.depth_stencil.depth.enabled) { + if (spu.read_depth) { wait_on_mask(1 << TAG_WRITE_TILE_Z); } } |