diff options
| author | Zack Rusin <zackr@vmware.com> | 2009-02-02 23:47:16 -0500 |
|---|---|---|
| committer | Zack Rusin <zackr@vmware.com> | 2009-02-02 23:47:16 -0500 |
| commit | 5069bfed29bcee2c89c36c74c6d65d388eb7792e (patch) | |
| tree | 2aef5035140ca24eef97b5d328e0c29d0460f3a8 /src/gallium/drivers/nv04/nv04_state_emit.c | |
| parent | df73c964d85d2f44d8c62558b5752b2f4443763f (diff) | |
gallium: remove pipe_buffer from surfaces
this change disassociates, at least from the driver perspective,
the surface from buffer. surfaces are technically now views on the
textures so make it so by hiding the buffer in the internals of
textures.
Diffstat (limited to 'src/gallium/drivers/nv04/nv04_state_emit.c')
| -rw-r--r-- | src/gallium/drivers/nv04/nv04_state_emit.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/gallium/drivers/nv04/nv04_state_emit.c b/src/gallium/drivers/nv04/nv04_state_emit.c index 26491758a0..bd8ef1adbf 100644 --- a/src/gallium/drivers/nv04/nv04_state_emit.c +++ b/src/gallium/drivers/nv04/nv04_state_emit.c @@ -96,6 +96,7 @@ static void nv04_state_emit_framebuffer(struct nv04_context* nv04) struct pipe_surface *rt, *zeta; uint32_t rt_format, w, h; int colour_format = 0, zeta_format = 0; + struct nv04_miptree *nv04mt = 0; w = fb->cbufs[0]->width; h = fb->cbufs[0]->height; @@ -129,14 +130,16 @@ static void nv04_state_emit_framebuffer(struct nv04_context* nv04) BEGIN_RING(context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_FORMAT, 1); OUT_RING(rt_format); - + + nv04mt = (struct nv04_miptree *)rt->texture; /* FIXME pitches have to be aligned ! */ BEGIN_RING(context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_PITCH, 2); OUT_RING(rt->stride|(zeta->stride<<16)); - OUT_RELOCl(rt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + OUT_RELOCl(nv04mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); if (fb->zsbuf) { + nv04mt = (struct nv04_miptree *)zeta->texture; BEGIN_RING(context_surfaces_3d, NV04_CONTEXT_SURFACES_3D_OFFSET_ZETA, 1); - OUT_RELOCl(zeta->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); + OUT_RELOCl(nv04mt->buffer, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR); } } |