i965g: more files compiling

7 files changed, 576 insertions, 322 deletions

diff --git a/src/gallium/drivers/i965/Makefile b/src/gallium/drivers/i965/Makefile
index ae37d2d702..d88f34cb7e 100644
--- a/src/gallium/drivers/i965/Makefile
+++ b/src/gallium/drivers/i965/Makefile
@@ -56,9 +56,9 @@ C_SOURCES = \
 	brw_wm_sampler_state.c \
 	brw_wm_state.c \
 	brw_wm_surface_state.c \
+	brw_screen_tex_layout.c \
 	brw_screen_surface.c \
 	brw_screen_texture.c \
-	brw_batchbuffer.c \
-	intel_tex_layout.c 
+	brw_batchbuffer.c 
 
 include ../../Makefile.template
diff --git a/src/gallium/drivers/i965/brw_defines.h b/src/gallium/drivers/i965/brw_defines.h
index 65cd71c939..92c6b6edc3 100644
--- a/src/gallium/drivers/i965/brw_defines.h
+++ b/src/gallium/drivers/i965/brw_defines.h
@@ -842,8 +842,5 @@
                                          (BRW_IS_G4X(brw) ? 384 : 256))  /* 512 bit units */
 
 
-#define BRW_TILING_NONE  0
-#define BRW_TILING_Y     1
-#define BRW_TILING_X     2
 
 #endif
diff --git a/src/gallium/drivers/i965/brw_screen.h b/src/gallium/drivers/i965/brw_screen.h
index 844c6355d5..bd04e689d9 100644
--- a/src/gallium/drivers/i965/brw_screen.h
+++ b/src/gallium/drivers/i965/brw_screen.h
@@ -65,6 +65,11 @@ struct brw_buffer
    boolean is_user_buffer;
 };
 
+#define BRW_TILING_NONE  0
+#define BRW_TILING_Y     1
+#define BRW_TILING_X     2
+
+
 struct brw_texture
 {
    struct pipe_texture base;
@@ -72,10 +77,17 @@ struct brw_texture
    struct brw_winsys_buffer *bo;
    struct brw_surface_state ss;
 
+   unsigned *image_offset[PIPE_MAX_TEXTURE_LEVELS];
+   unsigned nr_images[PIPE_MAX_TEXTURE_LEVELS];
+
+   unsigned level_offset[PIPE_MAX_TEXTURE_LEVELS];
+
+   boolean compressed;
    unsigned brw_target;
    unsigned pitch;
    unsigned tiling;
    unsigned cpp;
+   unsigned total_height;
 };
 
 
@@ -128,5 +140,13 @@ brw_surface_bo( struct pipe_surface *surface );
 unsigned
 brw_surface_pitch( const struct pipe_surface *surface );
 
+/***********************************************************************
+ * Internal functions 
+ */
+GLboolean brw_texture_layout(struct brw_screen *brw_screen,
+			     struct brw_texture *tex );
+
+
+
 
 #endif /* BRW_SCREEN_H */
diff --git a/src/gallium/drivers/i965/brw_screen_tex_layout.c b/src/gallium/drivers/i965/brw_screen_tex_layout.c
new file mode 100644
index 0000000000..8377d30564
--- /dev/null
+++ b/src/gallium/drivers/i965/brw_screen_tex_layout.c
@@ -0,0 +1,387 @@
+
+#include "pipe/p_format.h"
+
+#include "util/u_math.h"
+#include "util/u_memory.h"
+
+#include "brw_screen.h"
+#include "brw_debug.h"
+
+static int 
+brw_tex_pitch_align (struct brw_texture *tex,
+		     int pitch)
+{
+   if (!tex->compressed) {
+      int pitch_align;
+
+      switch (tex->tiling) {
+      case BRW_TILING_X:
+	 pitch_align = 512;
+	 break;
+      case BRW_TILING_Y:
+	 pitch_align = 128;
+	 break;
+      default:
+	 /* XXX: Untiled pitch alignment of 64 bytes for now to allow
+	  * render-to-texture to work in all cases. This should
+	  * probably be replaced at some point by some scheme to only
+	  * do this when really necessary, for example standalone
+	  * render target views.
+	  */
+	 pitch_align = 64;
+	 break;
+      }
+
+      pitch = align(pitch * tex->cpp, pitch_align);
+      pitch /= tex->cpp;
+   }
+
+   return pitch;
+}
+
+
+static void 
+brw_tex_alignment_unit(enum pipe_format pf, 
+		       GLuint *w, GLuint *h)
+{
+    switch (pf) {
+    case PIPE_FORMAT_DXT1_RGB:
+    case PIPE_FORMAT_DXT1_RGBA:
+    case PIPE_FORMAT_DXT3_RGBA:
+    case PIPE_FORMAT_DXT5_RGBA:
+    case PIPE_FORMAT_DXT1_SRGB:
+    case PIPE_FORMAT_DXT1_SRGBA:
+    case PIPE_FORMAT_DXT3_SRGBA:
+    case PIPE_FORMAT_DXT5_SRGBA:
+        *w = 4;
+        *h = 4;
+        break;
+
+    default:
+        *w = 4;
+        *h = 2;
+        break;
+    }
+}
+
+
+static void 
+brw_tex_set_level_info(struct brw_texture *tex,
+		       GLuint level,
+		       GLuint nr_images,
+		       GLuint x, GLuint y,
+		       GLuint w, GLuint h, GLuint d)
+{
+   assert(tex->base.width[level] == w);
+   assert(tex->base.height[level] == h);
+   assert(tex->base.depth[level] == d);
+   assert(tex->image_offset[level] == NULL);
+   assert(nr_images >= 1);
+
+   if (BRW_DEBUG & DEBUG_TEXTURE)
+      debug_printf("%s level %d size: %d,%d,%d offset %d,%d (0x%x)\n", __FUNCTION__,
+		   level, w, h, d, x, y, tex->level_offset[level]);
+
+
+   tex->level_offset[level] = (x + y * tex->pitch) * tex->cpp;
+   tex->nr_images[level] = nr_images;
+
+   tex->image_offset[level] = MALLOC(nr_images * sizeof(GLuint));
+   tex->image_offset[level][0] = 0;
+}
+
+
+static void
+brw_tex_set_image_offset(struct brw_texture *tex,
+			 GLuint level, GLuint img,
+			 GLuint x, GLuint y, 
+			 GLuint offset)
+{
+   assert((x == 0 && y == 0) || img != 0 || level != 0);
+   assert(img < tex->nr_images[level]);
+
+   if (BRW_DEBUG & DEBUG_TEXTURE)
+      debug_printf("%s level %d img %d pos %d,%d image_offset %x\n",
+		   __FUNCTION__, level, img, x, y, 
+		   tex->image_offset[level][img]);
+
+   tex->image_offset[level][img] = (x + y * tex->pitch) * tex->cpp + offset;
+}
+
+
+
+static void brw_layout_2d( struct brw_texture *tex )
+{
+   GLuint align_h = 2, align_w = 4;
+   GLuint level;
+   GLuint x = 0;
+   GLuint y = 0;
+   GLuint width = tex->base.width[0];
+   GLuint height = tex->base.height[0];
+
+   tex->pitch = tex->base.width[0];
+   brw_tex_alignment_unit(tex->base.format, &align_w, &align_h);
+
+   if (tex->compressed) {
+       tex->pitch = align(tex->base.width[0], align_w);
+   }
+
+   /* May need to adjust pitch to accomodate the placement of
+    * the 2nd mipmap.  This occurs when the alignment
+    * constraints of mipmap placement push the right edge of the
+    * 2nd mipmap out past the width of its parent.
+    */
+   if (tex->base.last_level > 0) {
+       GLuint mip1_width;
+
+       if (tex->compressed) {
+           mip1_width = align(minify(tex->base.width[0]), align_w)
+               + align(minify(minify(tex->base.width[0])), align_w);
+       } else {
+           mip1_width = align(minify(tex->base.width[0]), align_w)
+               + minify(minify(tex->base.width[0]));
+       }
+
+       if (mip1_width > tex->pitch) {
+           tex->pitch = mip1_width;
+       }
+   }
+
+   /* Pitch must be a whole number of dwords, even though we
+    * express it in texels.
+    */
+   tex->pitch = brw_tex_pitch_align (tex, tex->pitch);
+   tex->total_height = 0;
+
+   for ( level = 0 ; level <= tex->base.last_level ; level++ ) {
+      GLuint img_height;
+
+      brw_tex_set_level_info(tex, level, 1, x, y, width, height, 1);
+
+      if (tex->compressed)
+	 img_height = MAX2(1, height/4);
+      else
+	 img_height = align(height, align_h);
+
+
+      /* Because the images are packed better, the final offset
+       * might not be the maximal one:
+       */
+      tex->total_height = MAX2(tex->total_height, y + img_height);
+
+      /* Layout_below: step right after second mipmap.
+       */
+      if (level == 1) {
+	 x += align(width, align_w);
+      }
+      else {
+	 y += img_height;
+      }
+
+      width  = minify(width);
+      height = minify(height);
+   }
+}
+
+
+static boolean 
+brw_layout_cubemap_idgng( struct brw_texture *tex )
+{
+   GLuint align_h = 2, align_w = 4;
+   GLuint level;
+   GLuint x = 0;
+   GLuint y = 0;
+   GLuint width = tex->base.width[0];
+   GLuint height = tex->base.height[0];
+   GLuint qpitch = 0;
+   GLuint y_pitch = 0;
+
+   tex->pitch = tex->base.width[0];
+   brw_tex_alignment_unit(tex->base.format, &align_w, &align_h);
+   y_pitch = align(height, align_h);
+
+   if (tex->compressed) {
+      tex->pitch = align(tex->base.width[0], align_w);
+   }
+
+   if (tex->base.last_level != 0) {
+      GLuint mip1_width;
+
+      if (tex->compressed) {
+	 mip1_width = (align(minify(tex->base.width[0]), align_w) +
+		       align(minify(minify(tex->base.width[0])), align_w));
+      } else {
+	 mip1_width = (align(minify(tex->base.width[0]), align_w) +
+		       minify(minify(tex->base.width[0])));
+      }
+
+      if (mip1_width > tex->pitch) {
+	 tex->pitch = mip1_width;
+      }
+   }
+
+   tex->pitch = brw_tex_pitch_align(tex, tex->pitch);
+
+   if (tex->compressed) {
+      qpitch = ((y_pitch + 
+		 align(minify(y_pitch), align_h) +
+		 11 * align_h) / 4) * tex->pitch * tex->cpp;
+
+      tex->total_height = ((y_pitch + 
+			    align(minify(y_pitch), align_h) + 
+			    11 * align_h) / 4) * 6;
+   } else {
+      qpitch = (y_pitch + 
+		align(minify(y_pitch), align_h) + 
+		11 * align_h) * tex->pitch * tex->cpp;
+
+      tex->total_height = (y_pitch +
+			   align(minify(y_pitch), align_h) +
+			   11 * align_h) * 6;
+   }
+
+   for (level = 0; level <= tex->base.last_level; level++) {
+      GLuint img_height;
+      GLuint nr_images = 6;
+      GLuint q = 0;
+
+      brw_tex_set_level_info(tex, level, nr_images, x, y, width, height, 1);
+
+      for (q = 0; q < nr_images; q++)
+	 brw_tex_set_image_offset(tex, level, q, x, y, q * qpitch);
+
+      if (tex->compressed)
+	 img_height = MAX2(1, height/4);
+      else
+	 img_height = align(height, align_h);
+
+      if (level == 1) {
+	 x += align(width, align_w);
+      }
+      else {
+	 y += img_height;
+      }
+
+      width  = minify(width);
+      height = minify(height);
+   }
+
+   return TRUE;
+}
+
+
+static boolean
+brw_layout_3d_cube( struct brw_texture *tex )
+{
+   GLuint width  = tex->base.width[0];
+   GLuint height = tex->base.height[0];
+   GLuint depth = tex->base.depth[0];
+   GLuint pack_x_pitch, pack_x_nr;
+   GLuint pack_y_pitch;
+   GLuint level;
+   GLuint align_h = 2;
+   GLuint align_w = 4;
+
+   tex->total_height = 0;
+   brw_tex_alignment_unit(tex->base.format, &align_w, &align_h);
+
+   if (tex->compressed) {
+      tex->pitch = align(width, align_w);
+      pack_y_pitch = (height + 3) / 4;
+   } else {
+      tex->pitch = brw_tex_pitch_align(tex, tex->base.width[0]);
+      pack_y_pitch = align(tex->base.height[0], align_h);
+   }
+
+   pack_x_pitch = width;
+   pack_x_nr = 1;
+
+   for (level = 0 ; level <= tex->base.last_level ; level++) {
+      GLuint nr_images = tex->base.target == PIPE_TEXTURE_3D ? depth : 6;
+      GLint x = 0;
+      GLint y = 0;
+      GLint q, j;
+
+      brw_tex_set_level_info(tex, level, nr_images,
+				   0, tex->total_height,
+				   width, height, depth);
+
+      for (q = 0; q < nr_images;) {
+	 for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
+	    brw_tex_set_image_offset(tex, level, q, x, y, 0);
+	    x += pack_x_pitch;
+	 }
+
+	 x = 0;
+	 y += pack_y_pitch;
+      }
+
+
+      tex->total_height += y;
+      width  = minify(width);
+      height = minify(height);
+      depth  = minify(depth);
+
+      if (tex->compressed) {
+	 pack_y_pitch = (height + 3) / 4;
+
+	 if (pack_x_pitch > align(width, align_w)) {
+	    pack_x_pitch = align(width, align_w);
+	    pack_x_nr <<= 1;
+	 }
+      } else {
+	 if (pack_x_pitch > 4) {
+	    pack_x_pitch >>= 1;
+	    pack_x_nr <<= 1;
+	    assert(pack_x_pitch * pack_x_nr <= tex->pitch);
+	 }
+
+	 if (pack_y_pitch > 2) {
+	    pack_y_pitch >>= 1;
+	    pack_y_pitch = align(pack_y_pitch, align_h);
+	 }
+      }
+   }
+
+   /* The 965's sampler lays cachelines out according to how accesses
+    * in the texture surfaces run, so they may be "vertical" through
+    * memory.  As a result, the docs say in Surface Padding Requirements:
+    * Sampling Engine Surfaces that two extra rows of padding are required.
+    */
+   if (tex->base.target == PIPE_TEXTURE_CUBE)
+      tex->total_height += 2;
+
+   return TRUE;
+}
+
+
+
+GLboolean brw_texture_layout(struct brw_screen *brw_screen,
+			     struct brw_texture *tex )
+{
+   switch (tex->base.target) {
+   case PIPE_TEXTURE_CUBE:
+      if (brw_screen->chipset.is_igdng)
+	 brw_layout_cubemap_idgng( tex );
+      else
+	 brw_layout_3d_cube( tex );
+      break;
+	    
+   case PIPE_TEXTURE_3D:
+      brw_layout_3d_cube( tex );
+      break;
+
+   default:
+      brw_layout_2d( tex );
+      break;
+   }
+
+   if (BRW_DEBUG & DEBUG_TEXTURE)
+      debug_printf("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
+		   tex->pitch,
+		   tex->total_height,
+		   tex->cpp,
+		   tex->pitch * tex->total_height * tex->cpp );
+
+   return GL_TRUE;
+}
diff --git a/src/gallium/drivers/i965/brw_screen_texture.c b/src/gallium/drivers/i965/brw_screen_texture.c
index 3d069add6f..d527f22a8d 100644
--- a/src/gallium/drivers/i965/brw_screen_texture.c
+++ b/src/gallium/drivers/i965/brw_screen_texture.c
@@ -196,185 +196,6 @@ brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 }
 
 
-GLboolean brw_miptree_layout(struct brw_context *brw,
-			     struct intel_mipmap_tree *mt,
-			     uint32_t tiling)
-{
-   /* XXX: these vary depending on image format: */
-   /* GLint align_w = 4; */
-
-   switch (mt->target) {
-   case GL_TEXTURE_CUBE_MAP:
-      if (IS_IGDNG(brw->brw_screen->pci_id)) {
-          GLuint align_h = 2, align_w = 4;
-          GLuint level;
-          GLuint x = 0;
-          GLuint y = 0;
-          GLuint width = mt->width0;
-          GLuint height = mt->height0;
-          GLuint qpitch = 0;
-          GLuint y_pitch = 0;
-
-          mt->pitch = mt->width0;
-          intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-          y_pitch = ALIGN(height, align_h);
-
-          if (mt->compressed) {
-              mt->pitch = ALIGN(mt->width0, align_w);
-          }
-
-          if (mt->last_level != 0) {
-              GLuint mip1_width;
-
-              if (mt->compressed) {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + ALIGN(minify(minify(mt->width0)), align_w);
-              } else {
-                  mip1_width = ALIGN(minify(mt->width0), align_w)
-                      + minify(minify(mt->width0));
-              }
-
-              if (mip1_width > mt->pitch) {
-                  mt->pitch = mip1_width;
-              }
-          }
-
-          mt->pitch = intel_miptree_pitch_align(intel, mt, tiling, mt->pitch);
-
-          if (mt->compressed) {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * mt->pitch * mt->cpp;
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) / 4 * 6;
-          } else {
-              qpitch = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * mt->pitch * mt->cpp;
-              mt->total_height = (y_pitch + ALIGN(minify(y_pitch), align_h) + 11 * align_h) * 6;
-          }
-
-          for (level = 0; level <= mt->last_level; level++) {
-              GLuint img_height;
-              GLuint nr_images = 6;
-              GLuint q = 0;
-
-              intel_miptree_set_level_info(mt, level, nr_images, x, y, width, 
-                                           height, 1);
-
-              for (q = 0; q < nr_images; q++)
-                  intel_miptree_set_image_offset_ex(mt, level, q, x, y, q * qpitch);
-
-              if (mt->compressed)
-                  img_height = MAX2(1, height/4);
-              else
-                  img_height = ALIGN(height, align_h);
-
-              if (level == 1) {
-                  x += ALIGN(width, align_w);
-              }
-              else {
-                  y += img_height;
-              }
-
-              width  = minify(width);
-              height = minify(height);
-          }
-
-          break;
-      }
-
-   case GL_TEXTURE_3D: {
-      GLuint width  = mt->width0;
-      GLuint height = mt->height0;
-      GLuint depth = mt->depth0;
-      GLuint pack_x_pitch, pack_x_nr;
-      GLuint pack_y_pitch;
-      GLuint level;
-      GLuint align_h = 2;
-      GLuint align_w = 4;
-
-      mt->total_height = 0;
-      intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-
-      if (mt->compressed) {
-          mt->pitch = ALIGN(width, align_w);
-          pack_y_pitch = (height + 3) / 4;
-      } else {
-	 mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->width0);
-	 pack_y_pitch = ALIGN(mt->height0, align_h);
-      }
-
-      pack_x_pitch = width;
-      pack_x_nr = 1;
-
-      for (level = 0 ; level <= mt->last_level ; level++) {
-	 GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
-	 GLint x = 0;
-	 GLint y = 0;
-	 GLint q, j;
-
-	 intel_miptree_set_level_info(mt, level, nr_images,
-				      0, mt->total_height,
-				      width, height, depth);
-
-	 for (q = 0; q < nr_images;) {
-	    for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
-	       intel_miptree_set_image_offset(mt, level, q, x, y);
-	       x += pack_x_pitch;
-	    }
-
-	    x = 0;
-	    y += pack_y_pitch;
-	 }
-
-
-	 mt->total_height += y;
-	 width  = minify(width);
-	 height = minify(height);
-	 depth  = minify(depth);
-
-	 if (mt->compressed) {
-	    pack_y_pitch = (height + 3) / 4;
-
-	    if (pack_x_pitch > ALIGN(width, align_w)) {
-	       pack_x_pitch = ALIGN(width, align_w);
-	       pack_x_nr <<= 1;
-	    }
-	 } else {
-	    if (pack_x_pitch > 4) {
-	       pack_x_pitch >>= 1;
-	       pack_x_nr <<= 1;
-	       assert(pack_x_pitch * pack_x_nr <= mt->pitch);
-	    }
-
-	    if (pack_y_pitch > 2) {
-	       pack_y_pitch >>= 1;
-	       pack_y_pitch = ALIGN(pack_y_pitch, align_h);
-	    }
-	 }
-
-      }
-      /* The 965's sampler lays cachelines out according to how accesses
-       * in the texture surfaces run, so they may be "vertical" through
-       * memory.  As a result, the docs say in Surface Padding Requirements:
-       * Sampling Engine Surfaces that two extra rows of padding are required.
-       * We don't know of similar requirements for pre-965, but given that
-       * those docs are silent on padding requirements in general, let's play
-       * it safe.
-       */
-      if (mt->target == GL_TEXTURE_CUBE_MAP)
-	 mt->total_height += 2;
-      break;
-   }
-
-   default:
-      i945_miptree_layout_2d(intel, mt, tiling);
-      break;
-   }
-   DBG("%s: %dx%dx%d - sz 0x%x\n", __FUNCTION__,
-		mt->pitch,
-		mt->total_height,
-		mt->cpp,
-		mt->pitch * mt->total_height * mt->cpp );
-
-   return GL_TRUE;
-}
 
 
 static void brw_create_texture( struct pipe_screen *screen,
@@ -382,6 +203,21 @@ static void brw_create_texture( struct pipe_screen *screen,
 
 {  
 
+   tex->compressed = pf_is_compressed(tex->base.format);
+
+   if (intel->use_texture_tiling && compress_byte == 0 &&
+       intel->intelScreen->kernel_exec_fencing) {
+      if (IS_965(intel->intelScreen->deviceID) &&
+	  (base_format == GL_DEPTH_COMPONENT ||
+	   base_format == GL_DEPTH_STENCIL_EXT))
+	 tiling = I915_TILING_Y;
+      else
+	 tiling = I915_TILING_X;
+   } else
+      tiling = I915_TILING_NONE;
+
+
+
    key.format = tex->base.format;
    key.pitch = tex->pitch;
    key.depth = tex->base.depth[0];
@@ -389,7 +225,7 @@ static void brw_create_texture( struct pipe_screen *screen,
    key.offset = 0;
 
    key.target = tex->brw_target;	/* translated to BRW enum */
-   //key.depthmode = 0; /* XXX: add this to gallium? or the state tracker? */
+   //key.depthmode = 0; /* XXX: add this to gallium? or handle in the state tracker? */
    key.last_level = tex->base.last_level;
    key.width = tex->base.depth[0];
    key.height = tex->base.height[0];
diff --git a/src/gallium/drivers/i965/brw_wm_constant_buffer.c b/src/gallium/drivers/i965/brw_wm_constant_buffer.c
new file mode 100644
index 0000000000..7d2533b104
--- /dev/null
+++ b/src/gallium/drivers/i965/brw_wm_constant_buffer.c
@@ -0,0 +1,151 @@
+/* XXX: Constant buffers disabled
+ */
+
+
+/**
+ * Create the constant buffer surface.  Vertex/fragment shader constants will be
+ * read from this buffer with Data Port Read instructions/messages.
+ */
+struct brw_winsys_buffer *
+brw_create_constant_surface( struct brw_context *brw,
+                             struct brw_surface_key *key )
+{
+   const GLint w = key->width - 1;
+   struct brw_winsys_buffer *bo;
+
+   memset(&surf, 0, sizeof(surf));
+
+   surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
+   surf.ss0.surface_type = BRW_SURFACE_BUFFER;
+   surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+
+   assert(key->bo);
+   surf.ss1.base_addr = key->bo->offset; /* reloc */
+
+   surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
+   surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
+   surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
+   surf.ss3.pitch = (key->pitch * key->cpp) - 1; /* ignored?? */
+   brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
+ 
+   bo = brw_upload_cache(&brw->surface_cache, BRW_SS_SURFACE,
+			 key, sizeof(*key),
+			 &key->bo, key->bo ? 1 : 0,
+			 &surf, sizeof(surf),
+			 NULL, NULL);
+
+   if (key->bo) {
+      /* Emit relocation to surface contents */
+      brw->sws->bo_emit_reloc(bo,
+			      I915_GEM_DOMAIN_SAMPLER, 0,
+			      0,
+			      offsetof(struct brw_surface_state, ss1),
+			      key->bo);
+   }
+
+   return bo;
+}
+
+
+
+/**
+ * Update the surface state for a WM constant buffer.
+ * The constant buffer will be (re)allocated here if needed.
+ */
+static void
+brw_update_wm_constant_surface( struct brw_context *brw,
+                                GLuint surf)
+{
+   struct brw_surface_key key;
+   struct brw_fragment_shader *fp = brw->curr.fragment_shader;
+   struct pipe_buffer *cbuf = brw->curr.fragment_constants;
+   int pitch = cbuf->size / (4 * sizeof(float));
+
+   /* If we're in this state update atom, we need to update WM constants, so
+    * free the old buffer and create a new one for the new contents.
+    */
+   brw->sws->bo_unreference(fp->const_buffer);
+   fp->const_buffer = brw_wm_update_constant_buffer(brw);
+
+   /* If there's no constant buffer, then no surface BO is needed to point at
+    * it.
+    */
+   if (cbuf == NULL) {
+      drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
+      brw->wm.surf_bo[surf] = NULL;
+      return;
+   }
+
+   memset(&key, 0, sizeof(key));
+
+   key.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
+   key.ss0.surface_type = BRW_SURFACE_BUFFER;
+   key.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+
+   key.bo = brw_buffer(cbuf)->bo;
+
+   key.ss2.width = (pitch-1) & 0x7f;            /* bits 6:0 of size or width */
+   key.ss2.height = ((pitch-1) >> 7) & 0x1fff;  /* bits 19:7 of size or width */
+   key.ss3.depth = ((pitch-1) >> 20) & 0x7f;    /* bits 26:20 of size or width */
+   key.ss3.pitch = (pitch * 4 * sizeof(float)) - 1; /* ignored?? */
+   brw_set_surface_tiling(&surf, key->tiling); /* tiling now allowed */
+
+
+   /*
+   printf("%s:\n", __FUNCTION__);
+   printf("  width %d  height %d  depth %d  cpp %d  pitch %d\n",
+          key.width, key.height, key.depth, key.cpp, key.pitch);
+   */
+
+   brw->sws->bo_unreference(brw->wm.surf_bo[surf]);
+   brw->wm.surf_bo[surf] = brw_search_cache(&brw->surface_cache,
+                                            BRW_SS_SURFACE,
+                                            &key, sizeof(key),
+                                            &key.bo, 1,
+                                            NULL);
+   if (brw->wm.surf_bo[surf] == NULL) {
+      brw->wm.surf_bo[surf] = brw_create_constant_surface(brw, &key);
+   }
+   brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
+}
+
+/**
+ * Updates surface / buffer for fragment shader constant buffer, if
+ * one is required.
+ *
+ * This consumes the state updates for the constant buffer, and produces
+ * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
+ * inclusion in the binding table.
+ */
+static void prepare_wm_constant_surface(struct brw_context *brw )
+{
+   struct brw_fragment_program *fp =
+      (struct brw_fragment_program *) brw->fragment_program;
+   GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
+
+   drm_intel_bo_unreference(fp->const_buffer);
+   fp->const_buffer = brw_wm_update_constant_buffer(brw);
+
+   /* If there's no constant buffer, then no surface BO is needed to point at
+    * it.
+    */
+   if (fp->const_buffer == 0) {
+      if (brw->wm.surf_bo[surf] != NULL) {
+	 drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
+	 brw->wm.surf_bo[surf] = NULL;
+	 brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
+      }
+      return;
+   }
+
+   brw_update_wm_constant_surface(ctx, surf);
+}
+
+const struct brw_tracked_state brw_wm_constant_surface = {
+   .dirty = {
+      .mesa = (_NEW_PROGRAM_CONSTANTS),
+      .brw = (BRW_NEW_FRAGMENT_PROGRAM),
+      .cache = 0
+   },
+   .prepare = prepare_wm_constant_surface,
+};
diff --git a/src/gallium/drivers/i965/intel_tex_layout.c b/src/gallium/drivers/i965/intel_tex_layout.c
deleted file mode 100644
index 7e0ca553f2..0000000000
--- a/src/gallium/drivers/i965/intel_tex_layout.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/**************************************************************************
- * 
- * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- * 
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- * 
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- * 
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
- **************************************************************************/
- /*
-  * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
-  *   Michel Dänzer <michel@tungstengraphics.com>
-  */
-
-#include "intel_tex_layout.h"
-
-void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *h)
-{
-    switch (internalFormat) {
-    case GL_COMPRESSED_RGB_FXT1_3DFX:
-    case GL_COMPRESSED_RGBA_FXT1_3DFX:
-        *w = 8;
-        *h = 4;
-        break;
-
-    case GL_RGB_S3TC:
-    case GL_RGB4_S3TC:
-    case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
-    case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
-    case GL_RGBA_S3TC:
-    case GL_RGBA4_S3TC:
-    case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
-    case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
-        *w = 4;
-        *h = 4;
-        break;
-
-    default:
-        *w = 4;
-        *h = 2;
-        break;
-    }
-}
-
-void i945_miptree_layout_2d( struct intel_context *intel,
-			     struct intel_mipmap_tree *mt,
-			     uint32_t tiling )
-{
-   GLuint align_h = 2, align_w = 4;
-   GLuint level;
-   GLuint x = 0;
-   GLuint y = 0;
-   GLuint width = mt->width0;
-   GLuint height = mt->height0;
-
-   mt->pitch = mt->width0;
-   intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
-
-   if (mt->compressed) {
-       mt->pitch = ALIGN(mt->width0, align_w);
-   }
-
-   /* May need to adjust pitch to accomodate the placement of
-    * the 2nd mipmap.  This occurs when the alignment
-    * constraints of mipmap placement push the right edge of the
-    * 2nd mipmap out past the width of its parent.
-    */
-   if (mt->last_level) {
-       GLuint mip1_width;
-
-       if (mt->compressed) {
-           mip1_width = ALIGN(minify(mt->width0), align_w)
-               + ALIGN(minify(minify(mt->width0)), align_w);
-       } else {
-           mip1_width = ALIGN(minify(mt->width0), align_w)
-               + minify(minify(mt->width0));
-       }
-
-       if (mip1_width > mt->pitch) {
-           mt->pitch = mip1_width;
-       }
-   }
-
-   /* Pitch must be a whole number of dwords, even though we
-    * express it in texels.
-    */
-   mt->pitch = intel_miptree_pitch_align (intel, mt, tiling, mt->pitch);
-   mt->total_height = 0;
-
-   for ( level = 0 ; level <= mt->last_level ; level++ ) {
-      GLuint img_height;
-
-      intel_miptree_set_level_info(mt, level, 1, x, y, width, 
-				   height, 1);
-
-      if (mt->compressed)
-	 img_height = MAX2(1, height/4);
-      else
-	 img_height = ALIGN(height, align_h);
-
-
-      /* Because the images are packed better, the final offset
-       * might not be the maximal one:
-       */
-      mt->total_height = MAX2(mt->total_height, y + img_height);
-
-      /* Layout_below: step right after second mipmap.
-       */
-      if (level == 1) {
-	 x += ALIGN(width, align_w);
-      }
-      else {
-	 y += img_height;
-      }
-
-      width  = minify(width);
-      height = minify(height);
-   }
-}