diff options
author | Keith Whitwell <keithw@vmware.com> | 2009-12-21 19:18:41 +0000 |
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committer | Keith Whitwell <keithw@vmware.com> | 2009-12-21 19:18:41 +0000 |
commit | a5585cb533af3d4e5d5324d5f526447b98597402 (patch) | |
tree | 6706dbb8b4f994b919e247647c3e8853d067b45c /src/mesa/drivers/dri/i965/brw_draw.c | |
parent | d288a30610767f87e3e7c069730d4bc255246568 (diff) | |
parent | 574715d8368f99c0a5720a9676385d58d6cfdf30 (diff) |
Merge commit 'origin/master' into i965g-restart
Conflicts:
SConstruct
configs/default
configs/linux-dri
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 44bb7bd588..7ad860898f 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -145,7 +145,7 @@ static void brw_emit_prim(struct brw_context *brw, prim_packet.base_vert_location = prim->basevertex; /* Can't wrap here, since we rely on the validated state. */ - brw->no_batch_wrap = GL_TRUE; + intel->no_batch_wrap = GL_TRUE; /* If we're set to always flush, do it before and after the primitive emit. * We want to catch both missed flushes that hurt instruction/state cache @@ -153,21 +153,17 @@ static void brw_emit_prim(struct brw_context *brw, * the besides the draw code. */ if (intel->always_flush_cache) { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); - OUT_BATCH(intel->vtbl.flush_cmd()); - ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); } if (prim_packet.verts_per_instance) { intel_batchbuffer_data( brw->intel.batch, &prim_packet, sizeof(prim_packet), LOOP_CLIPRECTS); } if (intel->always_flush_cache) { - BEGIN_BATCH(1, IGNORE_CLIPRECTS); - OUT_BATCH(intel->vtbl.flush_cmd()); - ADVANCE_BATCH(); + intel_batchbuffer_emit_mi_flush(intel->batch); } - brw->no_batch_wrap = GL_FALSE; + intel->no_batch_wrap = GL_FALSE; } static void brw_merge_inputs( struct brw_context *brw, |