[965] Convert the driver to dri_bufmgr interface and enable TTM.

This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.

The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).

This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.

1 files changed, 37 insertions, 10 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 94d72839ff..2ade4eeae8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -142,7 +142,6 @@ static GLuint translate_tex_format( GLuint mesa_format )
 static
 void brw_update_texture_surface( GLcontext *ctx, GLuint unit )
 {
-   struct intel_context *intel = intel_context(ctx);
    struct brw_context *brw = brw_context(ctx);
    struct gl_texture_object *tObj = brw->attribs.Texture->Unit[unit]._Current;
    struct intel_texture_object *intelObj = intel_texture_object(tObj);
@@ -159,9 +158,8 @@ void brw_update_texture_surface( GLcontext *ctx, GLuint unit )
     */
 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 
-   /* BRW_NEW_LOCK */
-   surf.ss1.base_addr = bmBufferOffset(intel,
-					intelObj->mt->region->buffer);
+   /* Updated in emit_reloc */
+   surf.ss1.base_addr = intelObj->mt->region->buffer->offset;
 
    surf.ss2.mip_count = intelObj->lastLevel - intelObj->firstLevel;
    surf.ss2.width = firstImage->Width - 1;
@@ -221,9 +219,8 @@ static void upload_wm_surfaces(struct brw_context *brw )
       surf.ss0.writedisable_blue =  !brw->attribs.Color->ColorMask[2];
       surf.ss0.writedisable_alpha = !brw->attribs.Color->ColorMask[3];
 
-      /* BRW_NEW_LOCK */
-      surf.ss1.base_addr = bmBufferOffset(&brw->intel, region->buffer);
-
+      /* Updated in emit_reloc */
+      surf.ss1.base_addr = region->buffer->offset;
 
       surf.ss2.width = region->pitch - 1; /* XXX: not really! */
       surf.ss2.height = region->height - 1;
@@ -232,6 +229,7 @@ static void upload_wm_surfaces(struct brw_context *brw )
       surf.ss3.pitch = (region->pitch * region->cpp) - 1;
 
       brw->wm.bind.surf_ss_offset[0] = brw_cache_data( &brw->cache[BRW_SS_SURFACE], &surf );
+
       brw->wm.nr_surfaces = 1;
    }
 
@@ -262,14 +260,43 @@ static void upload_wm_surfaces(struct brw_context *brw )
 					    &brw->wm.bind );
 }
 
+static void emit_reloc_wm_surfaces(struct brw_context *brw)
+{
+   int unit;
+
+   /* Emit framebuffer relocation */
+   dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
+		  DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE,
+		  0,
+		  brw->wm.bind.surf_ss_offset[0] +
+		  offsetof(struct brw_surface_state, ss1),
+		  brw->state.draw_region->buffer);
+
+   /* Emit relocations for texture buffers */
+   for (unit = 0; unit < BRW_MAX_TEX_UNIT; unit++) {
+      struct gl_texture_unit *texUnit = &brw->attribs.Texture->Unit[unit];
+      struct gl_texture_object *tObj = texUnit->_Current;
+      struct intel_texture_object *intelObj = intel_texture_object(tObj);
+
+      if (texUnit->_ReallyEnabled && intelObj->mt != NULL) {
+	 dri_emit_reloc(brw_cache_buffer(brw, BRW_SS_SURFACE),
+			DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_READ,
+			0,
+			brw->wm.bind.surf_ss_offset[unit + 1] +
+			offsetof(struct brw_surface_state, ss1),
+			intelObj->mt->region->buffer);
+      }
+   }
+}
+
 const struct brw_tracked_state brw_wm_surfaces = {
    .dirty = {
       .mesa = _NEW_COLOR | _NEW_TEXTURE | _NEW_BUFFERS,
-      .brw = (BRW_NEW_CONTEXT | 
-	      BRW_NEW_LOCK),	/* required for bmBufferOffset */
+      .brw = BRW_NEW_CONTEXT,
       .cache = 0
    },
-   .update = upload_wm_surfaces
+   .update = upload_wm_surfaces,
+   .emit_reloc = emit_reloc_wm_surfaces,
 };