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authorNian Wu <nian.wu@intel.com>2007-03-13 17:00:18 +0800
committerNian Wu <nian.wu@intel.com>2007-03-13 17:00:18 +0800
commit4110fac38958003935f64e278d3a7b880523efe2 (patch)
tree1d123dcc2470c203d93a7918cb5a86fd25fd1e8a /src/mesa/drivers/dri/r300
parent5a5b55943dfdb7fac77f7556058791302ee8639b (diff)
parenteb4db4c4ec7efc366b00e1b1f1fe519ca1af79d6 (diff)
Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline
Diffstat (limited to 'src/mesa/drivers/dri/r300')
-rw-r--r--src/mesa/drivers/dri/r300/r300_cmdbuf.c3
-rw-r--r--src/mesa/drivers/dri/r300/r300_ioctl.c6
-rw-r--r--src/mesa/drivers/dri/r300/r300_reg.h7
-rw-r--r--src/mesa/drivers/dri/r300/r300_render.c12
-rw-r--r--src/mesa/drivers/dri/r300/radeon_mm.c2
5 files changed, 19 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index 89725447f1..e4511e0c21 100644
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -174,11 +174,12 @@ static __inline__ void r300DoEmitState(r300ContextPtr r300, GLboolean dirty)
dest ++;
r300->cmdbuf.count_used ++;
+ /* Emit cache flush */
*dest = cmdpacket0(R300_TX_CNTL, 1);
dest ++;
r300->cmdbuf.count_used ++;
- *dest = 0x0;
+ *dest = R300_TX_FLUSH;
dest ++;
r300->cmdbuf.count_used ++;
diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 6fa34ee482..f0741f978d 100644
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -162,11 +162,11 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer)
cmd2[8].u = r300PackFloat32(ctx->Color.ClearColor[3]);
reg_start(R300_RB3D_DSTCACHE_CTLSTAT,0);
- e32(0x0000000a);
+ e32(R300_RB3D_DSTCACHE_0A);
- reg_start(0x4f18,0);
- e32(0x00000003);
+ reg_start(R300_RB3D_ZCACHE_CTLSTAT,0);
+ e32(R300_RB3D_ZCACHE_CTLSTAT_03);
cp_wait(rmesa, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
}
diff --git a/src/mesa/drivers/dri/r300/r300_reg.h b/src/mesa/drivers/dri/r300/r300_reg.h
index 7bc832c871..f9accadf61 100644
--- a/src/mesa/drivers/dri/r300/r300_reg.h
+++ b/src/mesa/drivers/dri/r300/r300_reg.h
@@ -497,6 +497,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Zero to flush caches. */
#define R300_TX_CNTL 0x4100
+#define R300_TX_FLUSH 0x0
/* The upper enable bits are guessed, based on fglrx reported limits. */
#define R300_TX_ENABLE 0x4104
@@ -1395,6 +1396,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* gap */
+#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
+# define R300_RB3D_ZCACHE_CTLSTAT_01 0x1
+# define R300_RB3D_ZCACHE_CTLSTAT_03 0x3
+
+/* gap */
+
#define R300_RB3D_DEPTHOFFSET 0x4F20
#define R300_RB3D_DEPTHPITCH 0x4F24
# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */
diff --git a/src/mesa/drivers/dri/r300/r300_render.c b/src/mesa/drivers/dri/r300/r300_render.c
index 211c451f66..659ec3ff54 100644
--- a/src/mesa/drivers/dri/r300/r300_render.c
+++ b/src/mesa/drivers/dri/r300/r300_render.c
@@ -344,10 +344,10 @@ GLboolean r300_run_vb_render(GLcontext *ctx,
r300UpdateShaderStates(rmesa);
reg_start(R300_RB3D_DSTCACHE_CTLSTAT,0);
- e32(0x0000000a);
+ e32(R300_RB3D_DSTCACHE_0A);
- reg_start(0x4f18,0);
- e32(0x00000003);
+ reg_start(R300_RB3D_ZCACHE_CTLSTAT,0);
+ e32(R300_RB3D_ZCACHE_CTLSTAT_03);
r300EmitState(rmesa);
@@ -360,10 +360,10 @@ GLboolean r300_run_vb_render(GLcontext *ctx,
}
reg_start(R300_RB3D_DSTCACHE_CTLSTAT,0);
- e32(0x0000000a/*0x2*/);
+ e32(R300_RB3D_DSTCACHE_0A /*R300_RB3D_DSTCACHE_02*/);
- reg_start(0x4f18,0);
- e32(0x00000003/*0x1*/);
+ reg_start(R300_RB3D_ZCACHE_CTLSTAT,0);
+ e32(R300_RB3D_ZCACHE_CTLSTAT_03 /*R300_RB3D_ZCACHE_CTLSTAT_01*/);
#ifdef USER_BUFFERS
r300UseArrays(ctx);
diff --git a/src/mesa/drivers/dri/r300/radeon_mm.c b/src/mesa/drivers/dri/r300/radeon_mm.c
index 32ed1f4393..065f288e4c 100644
--- a/src/mesa/drivers/dri/r300/radeon_mm.c
+++ b/src/mesa/drivers/dri/r300/radeon_mm.c
@@ -284,7 +284,7 @@ static void emit_lin_cp(r300ContextPtr rmesa, unsigned long dst, unsigned long s
}
reg_start(R300_RB3D_DSTCACHE_CTLSTAT,0);
- e32(0x0000000a);
+ e32(R300_RB3D_DSTCACHE_0A);
reg_start(0x342c,0);
e32(0x00000005);