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authorAndre Maasikas <amaasikas@gmail.com>2009-12-08 10:16:14 +0200
committerAndre Maasikas <amaasikas@gmail.com>2009-12-08 10:16:14 +0200
commit0d4a05445c6b47b93269a3829afbe509ffec4817 (patch)
tree20bf88dcabe25cea87e1e084420111875f17ad72 /src/mesa/drivers/dri/r600/r700_assembler.c
parentba167f812c44c4bb8c8f844c3d5fbff60bfc93eb (diff)
parent369669ff9a7ff7636cadef8e2b13f2f28face98f (diff)
Merge branch 'mesa_7_6_branch' into mesa_7_7_branch
Diffstat (limited to 'src/mesa/drivers/dri/r600/r700_assembler.c')
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c26
1 files changed, 9 insertions, 17 deletions
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index e0d7d4fa6b..67e0ee7746 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -3915,22 +3915,6 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
need_barrier = GL_TRUE;
}
- switch (pAsm->pILInst[pAsm->uiCurInst].Opcode)
- {
- case OPCODE_TEX:
- break;
- case OPCODE_TXB:
- radeon_error("do not support TXB yet\n");
- return GL_FALSE;
- break;
- case OPCODE_TXP:
- break;
- default:
- radeon_error("Internal error: bad texture op (not TEX)\n");
- return GL_FALSE;
- break;
- }
-
if (pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXP)
{
GLuint tmp = gethelpr(pAsm);
@@ -4109,7 +4093,15 @@ GLboolean assemble_TEX(r700_AssemblerBase *pAsm)
}
- pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
+ if(pAsm->pILInst[pAsm->uiCurInst].Opcode == OPCODE_TXB)
+ {
+ pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE_L;
+ }
+ else
+ {
+ pAsm->D.dst.opcode = SQ_TEX_INST_SAMPLE;
+ }
+
pAsm->is_tex = GL_TRUE;
if ( GL_TRUE == need_barrier )
{