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authorCorbin Simpson <MostAwesomeDude@gmail.com>2010-01-11 20:41:57 -0800
committerCorbin Simpson <MostAwesomeDude@gmail.com>2010-01-11 20:54:12 -0800
commite920ee23b32f6031a7b8527b540566e7ada6af8a (patch)
treef8e0189a96eed71776c5cebfb8c3375427dacaa4 /src
parent22d615a9c4b95c528d6604eccb71cf6fe5193d5a (diff)
r300g: Placate kernel checker by explicitly disabling depth test.
This probably should disable stencil, too, if the kernel cares enough. Note: When atomized, framebuffer setup should go towards the end anyway, but it *must* follow these test setups anyway.
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/r300/r300_emit.c19
1 files changed, 8 insertions, 11 deletions
diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
index 0e5533c790..2bf8fbd684 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -122,15 +122,8 @@ void r300_emit_dsa_state(struct r300_context* r300, void* state)
}*/
OUT_CS_REG_SEQ(R300_ZB_CNTL, 3);
-
- if (r300->framebuffer_state.zsbuf) {
- OUT_CS(dsa->z_buffer_control);
- OUT_CS(dsa->z_stencil_control);
- } else {
- OUT_CS(0);
- OUT_CS(0);
- }
-
+ OUT_CS(dsa->z_buffer_control);
+ OUT_CS(dsa->z_stencil_control);
OUT_CS(dsa->stencil_ref_mask);
/* XXX it seems r3xx doesn't support STENCILREFMASK_BF */
@@ -395,7 +388,7 @@ void r300_emit_fb_state(struct r300_context* r300,
assert(fb->nr_cbufs <= 4);
BEGIN_CS((10 * fb->nr_cbufs) + (2 * (4 - fb->nr_cbufs)) +
- (fb->zsbuf ? 10 : 0) + 6);
+ (fb->zsbuf ? 10 : 3) + 6);
/* Flush and free renderbuffer caches. */
OUT_CS_REG(R300_RB3D_DSTCACHE_CTLSTAT,
@@ -431,7 +424,7 @@ void r300_emit_fb_state(struct r300_context* r300,
OUT_CS_REG(R300_US_OUT_FMT_0 + (4 * i), R300_US_OUT_FMT_UNUSED);
}
- /* Set up a zbuffer. */
+ /* Set up the Z/stencil buffer, or disable it. */
if (fb->zsbuf) {
surf = fb->zsbuf;
tex = (struct r300_texture*)surf->texture;
@@ -445,6 +438,10 @@ void r300_emit_fb_state(struct r300_context* r300,
OUT_CS_REG_SEQ(R300_ZB_DEPTHPITCH, 1);
OUT_CS_RELOC(tex->buffer, tex->pitch[surf->level], 0,
RADEON_GEM_DOMAIN_VRAM, 0);
+ } else {
+ OUT_CS_REG_SEQ(R300_ZB_CNTL, 2);
+ OUT_CS(0x0);
+ OUT_CS(0x0);
}
END_CS;