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path: root/src/mesa/drivers/dri/i965/brw_eu.h
AgeCommit message (Expand)Author
2009-11-06i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-30i965: use BRW_MAX_GRF, BRW_MAX_MRFBrian Paul
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
2009-05-12i965: increase BRW_EU_MAX_INSNBrian Paul
2009-04-17i915: fix broken indirect constant buffer readsBrian Paul
2009-04-16i965: implement relative addressing for VS constant buffer readsBrian Paul
2009-04-14i965: fix VS constant buffer readsBrian Paul
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
2009-04-03i965: added brw_same_reg()Brian Paul
2009-04-03i965: added new brw_dp_READ_4() functionBrian Paul
2009-03-13i965: more register number assertionsBrian Paul
2009-03-06i965: bump up BRW_EU_MAX_INSNBrian Paul
2009-02-13i965: rewrite the code for handling shader subroutine callsBrian Paul
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
2009-01-01i965: comments, clean-ups, re-order some functionsBrian Paul
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
2008-10-31i965: support destination horiz strides in align1 access mode.Gary Wong
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-04-25[i965] short immediate values must be replicated to both halves of the dwordKeith Packard
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-12-29fix fd.o bug #13847Zou Nan hai
2007-09-30 fragment shader function call fix, gl_FragCoord fixZou Nan hai
2007-09-29 support continue, fix conditionalZou Nan hai
2007-06-21 support branch and loop in pixel shaderZou Nan hai
2007-04-12 Initial 965 GLSL supportZou Nan hai
2007-02-23Update DRI drivers for new glsl compiler.Brian
2007-01-06i965: Avoid branch instructions while in single program flow mode.Eric Anholt
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
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