Mesa - My Mesa repository

Age	Commit message (Expand)	Author
2009-04-17	i915: fix broken indirect constant buffer reads	Brian Paul
2009-04-16	i965: implement relative addressing for VS constant buffer reads	Brian Paul
2009-04-14	i965: fix VS constant buffer reads	Brian Paul
2009-04-14	i965: checkpoint commit: VS constant buffers	Brian Paul
2009-04-09	i965: new SURF_INDEX_ macros	Brian Paul
2009-04-08	i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()	Brian Paul
2009-04-03	i965: s/GL_FALSE/BRW_COMPRESSION_NONE/	Brian Paul
2009-04-03	i965: fix response length param in brw_dp_READ_4()	Brian Paul
2009-04-03	i965: added new brw_dp_READ_4() function	Brian Paul
2009-04-03	i965: new and updated comments	Brian Paul
2009-04-03	i965: comments for brw_SAMPLE()	Brian Paul
2009-03-13	i965: add some register number assertions	Brian Paul
2009-02-13	i965: minor clean-ups	Brian Paul
2009-01-05	i965: implement OPCODE_TRUNC (round toward zero) on vertex path.	Brian Paul
2008-11-02	i965: Merge GM45 into the G4X chipset define.	Eric Anholt
2008-11-01	Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1	Keith Packard
2008-10-31	i965: support destination horiz strides in align1 access mode.	Gary Wong
2008-08-29	i965: force thread switch after IF/ELSE/ENDIF. partial fix for #16882.	Xiang, Haihao
2008-08-29	i965: mask control for BREAK/CONT/DO/WHILE. partial fix fox #16882	Xiang, Haihao
2008-07-08	i965: official name for GM45 chipset	Xiang, Haihao
2008-01-29	i965: new integrated graphics chipset support	Xiang, Haihao
2007-11-27	i965: The jump instruction count is added	Xiang, Haihao
2007-09-29	support continue, fix conditional	Zou Nan hai
2007-06-21	support branch and loop in pixel shader	Zou Nan hai
2007-04-12	Initial 965 GLSL support	Zou Nan hai
2007-01-06	i965: Avoid branch instructions while in single program flow mode.	Eric Anholt
2006-09-01	fix a couple of cases where a message reg is used as an instruction source.	Keith Whitwell
2006-08-09	Add Intel i965G/Q DRI driver.	Eric Anholt