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path: root/src/mesa/drivers/dri/i965/brw_misc_state.c
AgeCommit message (Expand)Author
2009-07-13i965: add support for new chipsetsXiang, Haihao
2009-06-23i965: Fix packed depth/stencil textures to be Y-tiled as well.Eric Anholt
2009-05-06i965: Disentangle VS constant surface state from WM surface state.Eric Anholt
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
2009-03-12i965: fix polygon stipple when rendering to FBORobert Ellison
2009-02-25i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.Eric Anholt
2009-02-02i965: Remove brw->attribs now that we can just always look in the GLcontext.Eric Anholt
2009-02-02i965: Delete old metaops code now that there are no remaining consumers.Eric Anholt
2008-11-02i965: Merge GM45 into the G4X chipset define.Eric Anholt
2008-10-28i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt
2008-10-28intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt
2008-10-24i965: don't emit state when dri_bufmgr_check_aperture_space fails.Xiang, Haihao
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
2008-08-08965: cleanups to state emission from aperture checking and state ordering.Eric Anholt
2008-07-25Merge branch 'master' into drm-gemIan Romanick
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
2008-05-07GEM: Remove already-disabled PIPE_CONTROL command.Eric Anholt
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
2008-04-18i965: fixup depth buffer checkDave Airlie
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
2008-02-07[965] Flush icache on new batch, not just new context.Eric Anholt
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-10[intel] Add more cliprect modes to cover other meanings for batch emits.Eric Anholt
2008-01-09[965] Replace the always_update dirty flag with BRW_NEW_BATCH.Eric Anholt
2008-01-09[965] Remove drawing rect upload, which is handled (better) by the kernel.Eric Anholt
2007-12-20[965] Enable EXT_framebuffer_object.Eric Anholt
2007-12-17[965] Allow draw or depth regions to be NULL.Eric Anholt
2007-12-14[965] Replace the state cache suballocator with direct dri_bufmgr use.Eric Anholt
2007-12-07[965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt
2006-12-08fix bug#9237Xiang, Haihao
2006-10-23Emit cliprects in the userspace driver as required, rather thanKeith Whitwell
2006-09-07Make sure bmBufferOffset is called for all active buffers every timeKeith Whitwell
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt